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From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: Lokesh Vutla <lokeshvutla@ti.com>,
	John Garry <john.garry@huawei.com>,
	linux-kernel@vger.kernel.org,
	Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges
Date: Tue,  6 Aug 2019 11:01:19 +0100	[thread overview]
Message-ID: <20190806100121.240767-11-maz@kernel.org> (raw)
In-Reply-To: <20190806100121.240767-1-maz@kernel.org>

As is it usual for the GIC, it isn't disallowed to put together a system
that is majorly inconsistent, with a distributor supporting the
extended ranges while some of the CPUs don't.

Kindly tell the user that things are sailing isn't going to be smooth.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 drivers/irqchip/irq-gic-v3.c       | 5 +++++
 include/linux/irqchip/arm-gic-v3.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index f53e58d398ba..334a10d9dbfb 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1014,6 +1014,11 @@ static void gic_cpu_init(void)
 
 	gic_enable_redist(true);
 
+	WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
+	     !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
+	     "Distributor has extended ranges, but CPU%d doesn't\n",
+	     smp_processor_id());
+
 	rbase = gic_data_rdist_sgi_base();
 
 	/* Configure SGIs/PPIs as non-secure Group-1 */
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 9ec3349dee04..5cc10cf7cb3e 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -496,6 +496,7 @@
 #define ICC_CTLR_EL1_A3V_SHIFT		15
 #define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
 #define ICC_CTLR_EL1_RSS		(0x1 << 18)
+#define ICC_CTLR_EL1_ExtRange		(0x1 << 19)
 #define ICC_PMR_EL1_SHIFT		0
 #define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
 #define ICC_BPR0_EL1_SHIFT		0
-- 
2.20.1


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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: John Garry <john.garry@huawei.com>,
	Shameerali Kolothum Thodi  <shameerali.kolothum.thodi@huawei.com>,
	Lokesh Vutla <lokeshvutla@ti.com>,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges
Date: Tue,  6 Aug 2019 11:01:19 +0100	[thread overview]
Message-ID: <20190806100121.240767-11-maz@kernel.org> (raw)
In-Reply-To: <20190806100121.240767-1-maz@kernel.org>

As is it usual for the GIC, it isn't disallowed to put together a system
that is majorly inconsistent, with a distributor supporting the
extended ranges while some of the CPUs don't.

Kindly tell the user that things are sailing isn't going to be smooth.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 drivers/irqchip/irq-gic-v3.c       | 5 +++++
 include/linux/irqchip/arm-gic-v3.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index f53e58d398ba..334a10d9dbfb 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1014,6 +1014,11 @@ static void gic_cpu_init(void)
 
 	gic_enable_redist(true);
 
+	WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
+	     !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
+	     "Distributor has extended ranges, but CPU%d doesn't\n",
+	     smp_processor_id());
+
 	rbase = gic_data_rdist_sgi_base();
 
 	/* Configure SGIs/PPIs as non-secure Group-1 */
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 9ec3349dee04..5cc10cf7cb3e 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -496,6 +496,7 @@
 #define ICC_CTLR_EL1_A3V_SHIFT		15
 #define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
 #define ICC_CTLR_EL1_RSS		(0x1 << 18)
+#define ICC_CTLR_EL1_ExtRange		(0x1 << 19)
 #define ICC_PMR_EL1_SHIFT		0
 #define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
 #define ICC_BPR0_EL1_SHIFT		0
-- 
2.20.1


  parent reply	other threads:[~2019-08-06 10:07 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-06 10:01 [PATCH v2 00/12] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Marc Zyngier
2019-08-06 10:01 ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 01/12] irqchip/gic: Rework gic_configure_irq to take the full ICFGR base Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-19 14:26   ` Zenghui Yu
2019-08-19 14:26     ` Zenghui Yu
2019-08-19 14:53     ` Marc Zyngier
2019-08-19 14:53       ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 02/12] irqchip/gic-v3: Add INTID range and convertion primitives Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 03/12] dt-bindings: interrupt-controller: arm, gic-v3: Describe ESPI range support Marc Zyngier
2019-08-06 10:01   ` [PATCH v2 03/12] dt-bindings: interrupt-controller: arm,gic-v3: " Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 04/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-19 14:25   ` Zenghui Yu
2019-08-19 14:25     ` Zenghui Yu
2019-08-20  9:18     ` Marc Zyngier
2019-08-20  9:18       ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 05/12] irqchip/gic: Prepare for more than 16 PPIs Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-21 18:40   ` Zenghui Yu
2019-08-21 18:40     ` Zenghui Yu
2019-08-22 16:11   ` Julien
2019-08-22 16:11     ` Julien
2019-08-22 16:32     ` Marc Zyngier
2019-08-22 16:32       ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 06/12] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-22 15:05   ` Julien
2019-08-22 15:05     ` Julien
2019-08-06 10:01 ` [PATCH v2 07/12] irqchip/gic-v3: Dynamically allocate PPI partition descriptors Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 08/12] dt-bindings: interrupt-controller: arm, gic-v3: Describe EPPI range support Marc Zyngier
2019-08-06 10:01   ` [PATCH v2 08/12] dt-bindings: interrupt-controller: arm,gic-v3: " Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 09/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-06 10:01 ` Marc Zyngier [this message]
2019-08-06 10:01   ` [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges Marc Zyngier
2019-08-06 10:15   ` Vladimir Murzin
2019-08-06 10:15     ` Vladimir Murzin
2019-08-06 11:15     ` Marc Zyngier
2019-08-06 11:15       ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 11/12] irqchip/gic: Skip DT quirks when evaluating IIDR-based quirks Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 12/12] irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803 Marc Zyngier
2019-08-06 10:01   ` Marc Zyngier
2019-08-06 11:07   ` John Garry
2019-08-06 11:07     ` John Garry

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