From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
mturquette@baylibre.com, robh+dt@kernel.org
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
haitao.suo@bitmain.com, darren.tsao@bitmain.com,
fisher.cheng@bitmain.com, alec.lin@bitmain.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: Re: [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
Date: Wed, 07 Aug 2019 22:01:28 -0700 [thread overview]
Message-ID: <20190808050128.E3DA52186A@mail.kernel.org> (raw)
In-Reply-To: <20190705151440.20844-2-manivannan.sadhasivam@linaro.org>
Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)
> Add devicetree binding for Bitmain BM1880 SoC clock controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++
Can you convert this to YAML? It's all the rage right now.
> include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++
> 2 files changed, 129 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> create mode 100644 include/dt-bindings/clock/bm1880-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> new file mode 100644
> index 000000000000..9c967095d430
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> @@ -0,0 +1,47 @@
> +* Bitmain BM1880 Clock Controller
> +
> +The Bitmain BM1880 clock controler generates and supplies clock to
> +various peripherals within the SoC.
> +
> +Required Properties:
> +
> +- compatible: Should be "bitmain,bm1880-clk"
> +- reg : Register address and size of PLL and SYS control domains
> +- reg-names : Register domain names: "pll" and "sys"
> +- clocks : Phandle of the input reference clock.
> +- #clock-cells: Should be 1.
> +
> +Each clock is assigned an identifier, and client nodes can use this identifier
> +to specify the clock which they consume.
> +
> +All available clocks are defined as preprocessor macros in corresponding
> +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources.
> +
> +External clocks:
> +
> +The osc clock used as the input for the plls is generated outside the SoC.
> +It is expected that it is defined using standard clock bindings as "osc".
> +
> +Example:
> +
> + clk: clock-controller@800 {
> + compatible = "bitmain,bm1880-clk";
> + reg = <0xe8 0x0c>,<0x800 0xb0>;
It looks weird still. What hardware module is this actually part of?
Some larger power manager block?
> + reg-names = "pll", "sys";
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
mturquette@baylibre.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
darren.tsao@bitmain.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, fisher.cheng@bitmain.com,
alec.lin@bitmain.com, linux-clk@vger.kernel.org,
haitao.suo@bitmain.com
Subject: Re: [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
Date: Wed, 07 Aug 2019 22:01:28 -0700 [thread overview]
Message-ID: <20190808050128.E3DA52186A@mail.kernel.org> (raw)
In-Reply-To: <20190705151440.20844-2-manivannan.sadhasivam@linaro.org>
Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)
> Add devicetree binding for Bitmain BM1880 SoC clock controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++
Can you convert this to YAML? It's all the rage right now.
> include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++
> 2 files changed, 129 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> create mode 100644 include/dt-bindings/clock/bm1880-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> new file mode 100644
> index 000000000000..9c967095d430
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> @@ -0,0 +1,47 @@
> +* Bitmain BM1880 Clock Controller
> +
> +The Bitmain BM1880 clock controler generates and supplies clock to
> +various peripherals within the SoC.
> +
> +Required Properties:
> +
> +- compatible: Should be "bitmain,bm1880-clk"
> +- reg : Register address and size of PLL and SYS control domains
> +- reg-names : Register domain names: "pll" and "sys"
> +- clocks : Phandle of the input reference clock.
> +- #clock-cells: Should be 1.
> +
> +Each clock is assigned an identifier, and client nodes can use this identifier
> +to specify the clock which they consume.
> +
> +All available clocks are defined as preprocessor macros in corresponding
> +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources.
> +
> +External clocks:
> +
> +The osc clock used as the input for the plls is generated outside the SoC.
> +It is expected that it is defined using standard clock bindings as "osc".
> +
> +Example:
> +
> + clk: clock-controller@800 {
> + compatible = "bitmain,bm1880-clk";
> + reg = <0xe8 0x0c>,<0x800 0xb0>;
It looks weird still. What hardware module is this actually part of?
Some larger power manager block?
> + reg-names = "pll", "sys";
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
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WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: mturquette@baylibre.com, robh+dt@kernel.org
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
haitao.suo@bitmain.com, darren.tsao@bitmain.com,
fisher.cheng@bitmain.com, alec.lin@bitmain.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: Re: [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
Date: Wed, 07 Aug 2019 22:01:28 -0700 [thread overview]
Message-ID: <20190808050128.E3DA52186A@mail.kernel.org> (raw)
In-Reply-To: <20190705151440.20844-2-manivannan.sadhasivam@linaro.org>
Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)
> Add devicetree binding for Bitmain BM1880 SoC clock controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++
Can you convert this to YAML? It's all the rage right now.
> include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++
> 2 files changed, 129 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> create mode 100644 include/dt-bindings/clock/bm1880-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> new file mode 100644
> index 000000000000..9c967095d430
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt
> @@ -0,0 +1,47 @@
> +* Bitmain BM1880 Clock Controller
> +
> +The Bitmain BM1880 clock controler generates and supplies clock to
> +various peripherals within the SoC.
> +
> +Required Properties:
> +
> +- compatible: Should be "bitmain,bm1880-clk"
> +- reg : Register address and size of PLL and SYS control domains
> +- reg-names : Register domain names: "pll" and "sys"
> +- clocks : Phandle of the input reference clock.
> +- #clock-cells: Should be 1.
> +
> +Each clock is assigned an identifier, and client nodes can use this identifier
> +to specify the clock which they consume.
> +
> +All available clocks are defined as preprocessor macros in corresponding
> +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources.
> +
> +External clocks:
> +
> +The osc clock used as the input for the plls is generated outside the SoC.
> +It is expected that it is defined using standard clock bindings as "osc".
> +
> +Example:
> +
> + clk: clock-controller@800 {
> + compatible = "bitmain,bm1880-clk";
> + reg = <0xe8 0x0c>,<0x800 0xb0>;
It looks weird still. What hardware module is this actually part of?
Some larger power manager block?
> + reg-names = "pll", "sys";
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
next prev parent reply other threads:[~2019-08-08 5:01 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 15:14 [PATCH 0/5] Add Bitmain BM1880 clock driver Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-07-05 15:14 ` [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-07-24 16:18 ` Rob Herring
2019-07-24 16:18 ` Rob Herring
2019-08-08 5:01 ` Stephen Boyd [this message]
2019-08-08 5:01 ` Stephen Boyd
2019-08-08 5:01 ` Stephen Boyd
2019-08-17 3:34 ` Manivannan Sadhasivam
2019-08-17 3:34 ` Manivannan Sadhasivam
2019-08-17 3:34 ` Manivannan Sadhasivam
2019-08-17 3:46 ` Stephen Boyd
2019-08-17 3:46 ` Stephen Boyd
2019-08-17 3:58 ` Manivannan Sadhasivam
2019-08-17 3:58 ` Manivannan Sadhasivam
2019-08-18 1:16 ` Stephen Boyd
2019-08-18 1:16 ` Stephen Boyd
2019-07-05 15:14 ` [PATCH 2/5] arm64: dts: bitmain: Add clock controller support for BM1880 SoC Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-07-05 15:14 ` [PATCH 3/5] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-07-05 15:14 ` [PATCH 4/5] clk: Add driver for Bitmain BM1880 SoC clock controller Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-08-08 5:15 ` Stephen Boyd
2019-08-08 5:15 ` Stephen Boyd
2019-08-08 5:15 ` Stephen Boyd
2019-08-17 3:55 ` Manivannan Sadhasivam
2019-08-17 3:55 ` Manivannan Sadhasivam
2019-08-18 1:21 ` Stephen Boyd
2019-08-18 1:21 ` Stephen Boyd
2019-07-05 15:14 ` [PATCH 5/5] MAINTAINERS: Add entry for Bitmain BM1880 SoC clock driver Manivannan Sadhasivam
2019-07-05 15:14 ` Manivannan Sadhasivam
2019-07-22 6:20 ` [PATCH 0/5] Add Bitmain BM1880 " Manivannan Sadhasivam
2019-07-22 6:20 ` Manivannan Sadhasivam
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