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From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com,
	kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
	digetx@gmail.com, mperttunen@nvidia.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
	mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support
Date: Mon, 12 Aug 2019 12:23:00 +0200	[thread overview]
Message-ID: <20190812102300.GM8903@ulmo> (raw)
In-Reply-To: <20190809044609.20401-13-vidyas@nvidia.com>

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On Fri, Aug 09, 2019 at 10:16:08AM +0530, Vidya Sagar wrote:
> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
> For each PCIe lane of a controller, there is a P2U unit instantiated at
> hardware level. This driver provides support for the programming required
> for each P2U that is going to be used for a PCIe controller.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> V15:
> * None
> 
> V14:
> * None
> 
> V13:
> * None
> 
> V12:
> * None
> 
> V11:
> * Replaced PTR_ERR_OR_ZERO() with PTR_ERR() as the check for zero is already
>   present in the code.
> 
> V10:
> * Used _relaxed() versions of readl() & writel()
> 
> V9:
> * Made it dependent on ARCH_TEGRA_194_SOC directly instead of ARCH_TEGRA
> 
> V8:
> * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
> 
> V7:
> * None
> 
> V6:
> * Addressed review comments from Thierry
> 
> V5:
> * None
> 
> V4:
> * Rebased on top of linux-next top of the tree
> 
> V3:
> * Replaced spaces with tabs in Kconfig file
> * Sorted header file inclusion alphabetically
> 
> V2:
> * Added COMPILE_TEST in Kconfig
> * Removed empty phy_ops implementations
> * Modified code according to DT documentation file modifications
> 
>  drivers/phy/tegra/Kconfig            |   7 ++
>  drivers/phy/tegra/Makefile           |   1 +
>  drivers/phy/tegra/phy-tegra194-p2u.c | 120 +++++++++++++++++++++++++++
>  3 files changed, 128 insertions(+)
>  create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c

Acked-by: Thierry Reding <treding@nvidia.com>

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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
	lorenzo.pieralisi@arm.com, mperttunen@nvidia.com,
	mmaddireddy@nvidia.com, linux-pci@vger.kernel.org,
	catalin.marinas@arm.com, will.deacon@arm.com,
	linux-kernel@vger.kernel.org, kthota@nvidia.com, kishon@ti.com,
	linux-tegra@vger.kernel.org, robh+dt@kernel.org,
	gustavo.pimentel@synopsys.com, jingoohan1@gmail.com,
	bhelgaas@google.com, digetx@gmail.com, jonathanh@nvidia.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support
Date: Mon, 12 Aug 2019 12:23:00 +0200	[thread overview]
Message-ID: <20190812102300.GM8903@ulmo> (raw)
In-Reply-To: <20190809044609.20401-13-vidyas@nvidia.com>


[-- Attachment #1.1: Type: text/plain, Size: 1732 bytes --]

On Fri, Aug 09, 2019 at 10:16:08AM +0530, Vidya Sagar wrote:
> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
> For each PCIe lane of a controller, there is a P2U unit instantiated at
> hardware level. This driver provides support for the programming required
> for each P2U that is going to be used for a PCIe controller.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> V15:
> * None
> 
> V14:
> * None
> 
> V13:
> * None
> 
> V12:
> * None
> 
> V11:
> * Replaced PTR_ERR_OR_ZERO() with PTR_ERR() as the check for zero is already
>   present in the code.
> 
> V10:
> * Used _relaxed() versions of readl() & writel()
> 
> V9:
> * Made it dependent on ARCH_TEGRA_194_SOC directly instead of ARCH_TEGRA
> 
> V8:
> * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
> 
> V7:
> * None
> 
> V6:
> * Addressed review comments from Thierry
> 
> V5:
> * None
> 
> V4:
> * Rebased on top of linux-next top of the tree
> 
> V3:
> * Replaced spaces with tabs in Kconfig file
> * Sorted header file inclusion alphabetically
> 
> V2:
> * Added COMPILE_TEST in Kconfig
> * Removed empty phy_ops implementations
> * Modified code according to DT documentation file modifications
> 
>  drivers/phy/tegra/Kconfig            |   7 ++
>  drivers/phy/tegra/Makefile           |   1 +
>  drivers/phy/tegra/phy-tegra194-p2u.c | 120 +++++++++++++++++++++++++++
>  3 files changed, 128 insertions(+)
>  create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c

Acked-by: Thierry Reding <treding@nvidia.com>

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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-08-12 10:23 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-09  4:45 [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09  4:45 ` Vidya Sagar
2019-08-09  4:45 ` Vidya Sagar
2019-08-09  4:45 ` [PATCH V15 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:45 ` [PATCH V15 02/13] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:45 ` [PATCH V15 03/13] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:45   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 04/13] PCI: dwc: Move config space capability search API Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 05/13] PCI: dwc: Add ext " Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 08/13] PCI: dwc: Add support to enable " Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 09/13] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46 ` [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-12 10:23   ` Thierry Reding [this message]
2019-08-12 10:23     ` Thierry Reding
2019-08-09  4:46 ` [PATCH V15 13/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-09  4:46   ` Vidya Sagar
2019-08-13 10:57   ` Lorenzo Pieralisi
2019-08-13 10:57     ` Lorenzo Pieralisi
2019-08-13 11:36     ` Vidya Sagar
2019-08-13 11:36       ` Vidya Sagar
2019-08-13 11:36       ` Vidya Sagar
2019-08-12 10:25 ` [PATCH V15 00/13] " Thierry Reding
2019-08-12 10:25   ` Thierry Reding
2019-08-12 10:29   ` Vidya Sagar
2019-08-12 10:29     ` Vidya Sagar
2019-08-12 10:29     ` Vidya Sagar
2019-08-12 10:34     ` Thierry Reding
2019-08-12 10:34       ` Thierry Reding

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