Re: [PATCH 7/8] drm/i915: Enhance cdclk sanitization

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Sep 06, 2019 at 05:21:42PM -0700, Matt Roper wrote:
> When reading out the BIOS-programmed cdclk state, let's make sure that
> the cdclk value is on the valid list for the platform, ensure that the
> VCO matches the cdclk, and ensure that the CD2X divider was set
> properly.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 34 ++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a6696697a09f..356495591cf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1607,6 +1607,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 cdctl, expected;
> +	int cdclk, vco;
>  
>  	intel_update_cdclk(dev_priv);
>  	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> @@ -1629,8 +1630,37 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	 */
>  	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
>  
> -	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> -		skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
> +	/* Make sure this is a legal cdclk value for the platform */
> +	cdclk = calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
> +	if (cdclk != dev_priv->cdclk.hw.cdclk)
> +		goto sanitize;
> +
> +	/* Make sure the VCO is correct for the cdclk */
> +	vco = calc_cdclk_pll_vco(dev_priv, cdclk);
> +	if (vco != dev_priv->cdclk.hw.vco)
> +		goto sanitize;
> +
> +	expected = skl_cdclk_decimal(cdclk);
> +
> +	/* Figure out what CD2X divider we should be using for this cdclk */
> +	switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
> +				  dev_priv->cdclk.hw.cdclk)) {
> +	case 2:
> +		expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
> +		break;
> +	case 3:
> +		expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
> +		break;
> +	case 4:
> +		expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
> +		break;
> +	case 8:
> +		expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
> +		break;
> +	default:
> +		goto sanitize;
> +	}
> +
>  	/*
>  	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
>  	 * enable otherwise.
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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