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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/8] drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
Date: Tue, 10 Sep 2019 15:39:45 +0300	[thread overview]
Message-ID: <20190910123945.GK7482@intel.com> (raw)
In-Reply-To: <20190907002143.22591-6-matthew.d.roper@intel.com>

On Fri, Sep 06, 2019 at 05:21:40PM -0700, Matt Roper wrote:
> The uninitialize flow is the same on all of these platforms, aside from
> calculating a different frequency level.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++++++---------------
>  1 file changed, 14 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f8c2a706990b..a70fec82d2bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1692,7 +1692,18 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  	cdclk_state.cdclk = cdclk_state.bypass;
>  	cdclk_state.vco = 0;
> -	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		cdclk_state.voltage_level =
> +			ehl_calc_voltage_level(cdclk_state.cdclk);
> +	else if (INTEL_GEN(dev_priv) >= 11)
> +		cdclk_state.voltage_level =
> +			icl_calc_voltage_level(cdclk_state.cdclk);
> +	else if (INTEL_GEN(dev_priv) >= 10)
> +		cdclk_state.voltage_level =
> +			cnl_calc_voltage_level(cdclk_state.cdclk);
> +	else
> +		cdclk_state.voltage_level =
> +			bxt_calc_voltage_level(cdclk_state.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
>  }
> @@ -1738,22 +1749,6 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
>  }
>  
> -static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> -
> -	cdclk_state.cdclk = cdclk_state.bypass;
> -	cdclk_state.vco = 0;
> -	if (IS_ELKHARTLAKE(dev_priv))
> -		cdclk_state.voltage_level =
> -			ehl_calc_voltage_level(cdclk_state.cdclk);
> -	else
> -		cdclk_state.voltage_level =
> -			icl_calc_voltage_level(cdclk_state.cdclk);
> -
> -	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> -}
> -
>  static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state cdclk_state;
> @@ -1773,17 +1768,6 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
>  }
>  
> -static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> -
> -	cdclk_state.cdclk = cdclk_state.bypass;
> -	cdclk_state.vco = 0;
> -	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
> -
> -	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> -}
> -
>  /**
>   * intel_cdclk_init - Initialize CDCLK
>   * @i915: i915 device
> @@ -1814,14 +1798,10 @@ void intel_cdclk_init(struct drm_i915_private *i915)
>   */
>  void intel_cdclk_uninit(struct drm_i915_private *i915)
>  {
> -	if (INTEL_GEN(i915) >= 11)
> -		icl_uninit_cdclk(i915);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_uninit_cdclk(i915);
> +	if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)

I think the general concensus has been to list platforms
from new to old. Might be good to stick to that even
within conditions like this. There may have been other cases like this
in these patches that I didn't spot.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +		bxt_uninit_cdclk(i915);
>  	else if (IS_GEN9_BC(i915))
>  		skl_uninit_cdclk(i915);
> -	else if (IS_GEN9_LP(i915))
> -		bxt_uninit_cdclk(i915);
>  }
>  
>  /**
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-09-10 12:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-07  0:21 [PATCH 0/8] cdclk consolidation and rework for BXT-TGL Matt Roper
2019-09-07  0:21 ` [PATCH 1/8] drm/i915: Consolidate bxt/cnl/icl cdclk readout Matt Roper
2019-09-10 12:27   ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 2/8] drm/i915: Use literal representation of cdclk tables Matt Roper
2019-09-08  2:57   ` Matt Roper
2019-09-08  4:05     ` Matt Roper
2019-09-10 12:56       ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 3/8] drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk Matt Roper
2019-09-10 12:35   ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 4/8] drm/i915: Kill cnl_sanitize_cdclk() Matt Roper
2019-09-10 12:37   ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 5/8] drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk Matt Roper
2019-09-10 12:39   ` Ville Syrjälä [this message]
2019-09-07  0:21 ` [PATCH 6/8] drm/i915: Add calc_voltage_level display vfunc Matt Roper
2019-09-10 12:41   ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 7/8] drm/i915: Enhance cdclk sanitization Matt Roper
2019-09-10 12:42   ` Ville Syrjälä
2019-09-07  0:21 ` [PATCH 8/8] drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk Matt Roper
2019-09-10 12:44   ` Ville Syrjälä
2019-09-07  0:43 ` ✗ Fi.CI.CHECKPATCH: warning for cdclk consolidation and rework for BXT-TGL Patchwork
2019-09-07  1:31 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-09-08  3:17 ` ✗ Fi.CI.BUILD: failure for cdclk consolidation and rework for BXT-TGL (rev2) Patchwork
2019-09-08  4:23 ` ✗ Fi.CI.CHECKPATCH: warning for cdclk consolidation and rework for BXT-TGL (rev3) Patchwork
2019-09-08  4:48 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-08  5:57 ` ✓ Fi.CI.IGT: " Patchwork

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