From: Nicolin Chen <nicoleotsuka@gmail.com>
To: "S.j. Wang" <shengjiu.wang@nxp.com>
Cc: "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"timur@kernel.org" <timur@kernel.org>,
"Xiubo.Lee@gmail.com" <Xiubo.Lee@gmail.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"tiwai@suse.com" <tiwai@suse.com>,
"lgirdwood@gmail.com" <lgirdwood@gmail.com>,
"broonie@kernel.org" <broonie@kernel.org>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [alsa-devel] [PATCH 2/3] ASoC: fsl_asrc: update supported sample format
Date: Thu, 12 Sep 2019 16:51:03 -0700 [thread overview]
Message-ID: <20190912235103.GD24937@Asurada-Nvidia.nvidia.com> (raw)
In-Reply-To: <VE1PR04MB64791308D87F91C51412DF53E3B60@VE1PR04MB6479.eurprd04.prod.outlook.com>
On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote:
> > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote:
> > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format
> > > should not be supported, it is word width is 20bit.
> >
> > I thought 3LE used 24-bit physical width. And the driver assigns
> > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit would go
> > for that 24-bit slot also. I don't clearly recall if I had explicitly tested
> > S20_3LE, but I feel it should work since I put there...
>
> For S20_3LE, the width is 20bit, but the ASRC only support 24bit, if set the
> ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the volume is
> Lower than expected, it likes 24bit data right shift 4 bit.
> So it is not supported.
Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought
they're left aligned...
If this is the case...shouldn't we have the same lower-volume
problem for all hardwares that support S20_3LE now?
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WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: "S.j. Wang" <shengjiu.wang@nxp.com>
Cc: "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"timur@kernel.org" <timur@kernel.org>,
"Xiubo.Lee@gmail.com" <Xiubo.Lee@gmail.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"tiwai@suse.com" <tiwai@suse.com>,
"lgirdwood@gmail.com" <lgirdwood@gmail.com>,
"perex@perex.cz" <perex@perex.cz>,
"broonie@kernel.org" <broonie@kernel.org>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] ASoC: fsl_asrc: update supported sample format
Date: Thu, 12 Sep 2019 16:51:03 -0700 [thread overview]
Message-ID: <20190912235103.GD24937@Asurada-Nvidia.nvidia.com> (raw)
In-Reply-To: <VE1PR04MB64791308D87F91C51412DF53E3B60@VE1PR04MB6479.eurprd04.prod.outlook.com>
On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote:
> > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote:
> > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format
> > > should not be supported, it is word width is 20bit.
> >
> > I thought 3LE used 24-bit physical width. And the driver assigns
> > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit would go
> > for that 24-bit slot also. I don't clearly recall if I had explicitly tested
> > S20_3LE, but I feel it should work since I put there...
>
> For S20_3LE, the width is 20bit, but the ASRC only support 24bit, if set the
> ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the volume is
> Lower than expected, it likes 24bit data right shift 4 bit.
> So it is not supported.
Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought
they're left aligned...
If this is the case...shouldn't we have the same lower-volume
problem for all hardwares that support S20_3LE now?
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: "S.j. Wang" <shengjiu.wang@nxp.com>
Cc: "timur@kernel.org" <timur@kernel.org>,
"Xiubo.Lee@gmail.com" <Xiubo.Lee@gmail.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"lgirdwood@gmail.com" <lgirdwood@gmail.com>,
"broonie@kernel.org" <broonie@kernel.org>,
"perex@perex.cz" <perex@perex.cz>,
"tiwai@suse.com" <tiwai@suse.com>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] ASoC: fsl_asrc: update supported sample format
Date: Thu, 12 Sep 2019 16:51:03 -0700 [thread overview]
Message-ID: <20190912235103.GD24937@Asurada-Nvidia.nvidia.com> (raw)
In-Reply-To: <VE1PR04MB64791308D87F91C51412DF53E3B60@VE1PR04MB6479.eurprd04.prod.outlook.com>
On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote:
> > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote:
> > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format
> > > should not be supported, it is word width is 20bit.
> >
> > I thought 3LE used 24-bit physical width. And the driver assigns
> > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit would go
> > for that 24-bit slot also. I don't clearly recall if I had explicitly tested
> > S20_3LE, but I feel it should work since I put there...
>
> For S20_3LE, the width is 20bit, but the ASRC only support 24bit, if set the
> ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the volume is
> Lower than expected, it likes 24bit data right shift 4 bit.
> So it is not supported.
Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought
they're left aligned...
If this is the case...shouldn't we have the same lower-volume
problem for all hardwares that support S20_3LE now?
next prev parent reply other threads:[~2019-09-12 23:52 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-10 2:07 [alsa-devel] [PATCH 2/3] ASoC: fsl_asrc: update supported sample format S.j. Wang
2019-09-10 2:07 ` S.j. Wang
2019-09-10 2:07 ` S.j. Wang
2019-09-12 23:51 ` Nicolin Chen [this message]
2019-09-12 23:51 ` Nicolin Chen
2019-09-12 23:51 ` Nicolin Chen
2019-09-13 5:48 ` [alsa-devel] [EXT] " S.j. Wang
2019-09-13 5:48 ` S.j. Wang
2019-09-13 5:48 ` S.j. Wang
2019-09-16 22:42 ` [alsa-devel] " Nicolin Chen
2019-09-16 22:42 ` Nicolin Chen
2019-09-16 22:42 ` Nicolin Chen
-- strict thread matches above, loose matches on Subject: below --
2019-09-18 2:58 [alsa-devel] " S.j. Wang
2019-09-09 22:33 [alsa-devel] [PATCH 0/3] " Shengjiu Wang
2019-09-09 22:33 ` [alsa-devel] [PATCH 2/3] ASoC: fsl_asrc: " Shengjiu Wang
2019-09-09 20:19 ` Nicolin Chen
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