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From: Stephen Boyd <sboyd@kernel.org>
To: "festevam@gmail.com" <festevam@gmail.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Peng Fan <peng.fan@nxp.com>
Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>,
	dl-linux-imx <linux-imx@nxp.com>,
	Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
	Abel Vesa <abel.vesa@nxp.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Leonard Crestez <leonard.crestez@nxp.com>,
	Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH V3 1/4] clk: imx: pll14xx: avoid glitch when set rate
Date: Tue, 17 Sep 2019 23:07:22 -0700	[thread overview]
Message-ID: <20190918060723.61E0120856@mail.kernel.org> (raw)
In-Reply-To: <1568043491-20680-2-git-send-email-peng.fan@nxp.com>

Quoting Peng Fan (2019-09-08 20:39:34)
> From: Peng Fan <peng.fan@nxp.com>
> 
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
> 
> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> In the end of set rate, BYPASS will be cleared.
> 
> When prepare clock, also need to take care to avoid glitch. So
> we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
> And add a check if the RESETB is already 0, directly return 0;
> 
> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---

Applied to clk-next


WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: "festevam@gmail.com" <festevam@gmail.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Peng Fan <peng.fan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>, Abel Vesa <abel.vesa@nxp.com>,
	Anson Huang <anson.huang@nxp.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	dl-linux-imx <linux-imx@nxp.com>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	Leonard Crestez <leonard.crestez@nxp.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH V3 1/4] clk: imx: pll14xx: avoid glitch when set rate
Date: Tue, 17 Sep 2019 23:07:22 -0700	[thread overview]
Message-ID: <20190918060723.61E0120856@mail.kernel.org> (raw)
In-Reply-To: <1568043491-20680-2-git-send-email-peng.fan@nxp.com>

Quoting Peng Fan (2019-09-08 20:39:34)
> From: Peng Fan <peng.fan@nxp.com>
> 
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
> 
> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> In the end of set rate, BYPASS will be cleared.
> 
> When prepare clock, also need to take care to avoid glitch. So
> we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
> And add a check if the RESETB is already 0, directly return 0;
> 
> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---

Applied to clk-next


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  reply	other threads:[~2019-09-18  6:07 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-09  3:39 [PATCH V3 0/4] clk: imx8m: fix glitch/mux Peng Fan
2019-09-09  3:39 ` Peng Fan
2019-09-09  3:39 ` [PATCH V3 1/4] clk: imx: pll14xx: avoid glitch when set rate Peng Fan
2019-09-09  3:39   ` Peng Fan
2019-09-18  6:07   ` Stephen Boyd [this message]
2019-09-18  6:07     ` Stephen Boyd
2019-09-09  3:39 ` [PATCH V3 2/4] clk: imx: clk-pll14xx: unbypass PLL by default Peng Fan
2019-09-09  3:39   ` Peng Fan
2019-09-18  6:07   ` Stephen Boyd
2019-09-18  6:07     ` Stephen Boyd
2019-09-09  3:39 ` [PATCH V3 3/4] clk: imx: imx8mm: fix pll mux bit Peng Fan
2019-09-09  3:39   ` Peng Fan
2019-09-18  6:07   ` Stephen Boyd
2019-09-18  6:07     ` Stephen Boyd
2019-09-09  3:39 ` [PATCH V3 4/4] clk: imx: imx8mn: " Peng Fan
2019-09-09  3:39   ` Peng Fan
2019-09-18  6:07   ` Stephen Boyd
2019-09-18  6:07     ` Stephen Boyd
2019-09-17  6:20 ` [PATCH V3 0/4] clk: imx8m: fix glitch/mux Peng Fan
2019-09-17  6:20   ` Peng Fan
2019-09-17 16:28   ` Stephen Boyd
2019-09-17 16:28     ` Stephen Boyd
2019-09-18  5:45     ` Peng Fan
2019-09-18  5:45       ` Peng Fan
2019-09-18  5:53       ` Stephen Boyd
2019-09-18  5:53         ` Stephen Boyd

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