From: kbuild test robot <lkp@intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, kbuild-all@01.org,
stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3.
Date: Mon, 23 Sep 2019 22:22:27 +0800 [thread overview]
Message-ID: <201909232212.MSDmMJOL%lkp@intel.com> (raw)
In-Reply-To: <20190923125252.25913-1-maarten.lankhorst@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 7236 bytes --]
Hi Maarten,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3 next-20190920]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-i915-dp-Fix-dsc-bpp-calculations-v3/20190923-205540
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-13) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config':
>> drivers/gpu/drm/i915/display/intel_ddi.c:3905:17: error: implicit declaration of function 'TGL_DP_TP_CTL'; did you mean 'DP_TP_CTL'? [-Werror=implicit-function-declaration]
dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
^~~~~~~~~~~~~
DP_TP_CTL
>> drivers/gpu/drm/i915/display/intel_ddi.c:3905:15: error: incompatible types when assigning to type 'i915_reg_t {aka struct <anonymous>}' from type 'int'
dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
^
cc1: some warnings being treated as errors
vim +3905 drivers/gpu/drm/i915/display/intel_ddi.c
3826
3827 void intel_ddi_get_config(struct intel_encoder *encoder,
3828 struct intel_crtc_state *pipe_config)
3829 {
3830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3831 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3832 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3833 u32 temp, flags = 0;
3834
3835 /* XXX: DSI transcoder paranoia */
3836 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3837 return;
3838
3839 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3840 if (temp & TRANS_DDI_PHSYNC)
3841 flags |= DRM_MODE_FLAG_PHSYNC;
3842 else
3843 flags |= DRM_MODE_FLAG_NHSYNC;
3844 if (temp & TRANS_DDI_PVSYNC)
3845 flags |= DRM_MODE_FLAG_PVSYNC;
3846 else
3847 flags |= DRM_MODE_FLAG_NVSYNC;
3848
3849 pipe_config->base.adjusted_mode.flags |= flags;
3850
3851 switch (temp & TRANS_DDI_BPC_MASK) {
3852 case TRANS_DDI_BPC_6:
3853 pipe_config->pipe_bpp = 18;
3854 break;
3855 case TRANS_DDI_BPC_8:
3856 pipe_config->pipe_bpp = 24;
3857 break;
3858 case TRANS_DDI_BPC_10:
3859 pipe_config->pipe_bpp = 30;
3860 break;
3861 case TRANS_DDI_BPC_12:
3862 pipe_config->pipe_bpp = 36;
3863 break;
3864 default:
3865 break;
3866 }
3867
3868 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3869 case TRANS_DDI_MODE_SELECT_HDMI:
3870 pipe_config->has_hdmi_sink = true;
3871
3872 pipe_config->infoframes.enable |=
3873 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3874
3875 if (pipe_config->infoframes.enable)
3876 pipe_config->has_infoframe = true;
3877
3878 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3879 pipe_config->hdmi_scrambling = true;
3880 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3881 pipe_config->hdmi_high_tmds_clock_ratio = true;
3882 /* fall through */
3883 case TRANS_DDI_MODE_SELECT_DVI:
3884 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3885 pipe_config->lane_count = 4;
3886 break;
3887 case TRANS_DDI_MODE_SELECT_FDI:
3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3889 break;
3890 case TRANS_DDI_MODE_SELECT_DP_SST:
3891 if (encoder->type == INTEL_OUTPUT_EDP)
3892 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3893 else
3894 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3895 pipe_config->lane_count =
3896 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3897 intel_dp_get_m_n(intel_crtc, pipe_config);
3898
3899 if (INTEL_GEN(dev_priv) >= 11) {
3900 i915_reg_t dp_tp_ctl;
3901
3902 if (IS_GEN(dev_priv, 11))
3903 dp_tp_ctl = DP_TP_CTL(pipe_config->cpu_transcoder);
3904 else
> 3905 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
3906
3907 pipe_config->fec_enable =
3908 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3909
3910 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
3911 encoder->base.base.id, encoder->base.name,
3912 pipe_config->fec_enable);
3913 }
3914
3915 break;
3916 case TRANS_DDI_MODE_SELECT_DP_MST:
3917 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3918 pipe_config->lane_count =
3919 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3920 intel_dp_get_m_n(intel_crtc, pipe_config);
3921 break;
3922 default:
3923 break;
3924 }
3925
3926 pipe_config->has_audio =
3927 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3928
3929 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3930 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3931 /*
3932 * This is a big fat ugly hack.
3933 *
3934 * Some machines in UEFI boot mode provide us a VBT that has 18
3935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3936 * unknown we fail to light up. Yet the same BIOS boots up with
3937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3938 * max, not what it tells us to use.
3939 *
3940 * Note: This will still be broken if the eDP panel is not lit
3941 * up by the BIOS, and thus we can't get the mode at module
3942 * load.
3943 */
3944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3945 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3946 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3947 }
3948
3949 intel_ddi_clock_get(encoder, pipe_config);
3950
3951 if (IS_GEN9_LP(dev_priv))
3952 pipe_config->lane_lat_optim_mask =
3953 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3954
3955 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3956
3957 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3958
3959 intel_read_infoframe(encoder, pipe_config,
3960 HDMI_INFOFRAME_TYPE_AVI,
3961 &pipe_config->infoframes.avi);
3962 intel_read_infoframe(encoder, pipe_config,
3963 HDMI_INFOFRAME_TYPE_SPD,
3964 &pipe_config->infoframes.spd);
3965 intel_read_infoframe(encoder, pipe_config,
3966 HDMI_INFOFRAME_TYPE_VENDOR,
3967 &pipe_config->infoframes.hdmi);
3968 intel_read_infoframe(encoder, pipe_config,
3969 HDMI_INFOFRAME_TYPE_DRM,
3970 &pipe_config->infoframes.drm);
3971 }
3972
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp@intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: kbuild-all@01.org, intel-gfx@lists.freedesktop.org,
stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3.
Date: Mon, 23 Sep 2019 22:22:27 +0800 [thread overview]
Message-ID: <201909232212.MSDmMJOL%lkp@intel.com> (raw)
In-Reply-To: <20190923125252.25913-1-maarten.lankhorst@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 7236 bytes --]
Hi Maarten,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3 next-20190920]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-i915-dp-Fix-dsc-bpp-calculations-v3/20190923-205540
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-13) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config':
>> drivers/gpu/drm/i915/display/intel_ddi.c:3905:17: error: implicit declaration of function 'TGL_DP_TP_CTL'; did you mean 'DP_TP_CTL'? [-Werror=implicit-function-declaration]
dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
^~~~~~~~~~~~~
DP_TP_CTL
>> drivers/gpu/drm/i915/display/intel_ddi.c:3905:15: error: incompatible types when assigning to type 'i915_reg_t {aka struct <anonymous>}' from type 'int'
dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
^
cc1: some warnings being treated as errors
vim +3905 drivers/gpu/drm/i915/display/intel_ddi.c
3826
3827 void intel_ddi_get_config(struct intel_encoder *encoder,
3828 struct intel_crtc_state *pipe_config)
3829 {
3830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3831 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3832 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3833 u32 temp, flags = 0;
3834
3835 /* XXX: DSI transcoder paranoia */
3836 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3837 return;
3838
3839 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3840 if (temp & TRANS_DDI_PHSYNC)
3841 flags |= DRM_MODE_FLAG_PHSYNC;
3842 else
3843 flags |= DRM_MODE_FLAG_NHSYNC;
3844 if (temp & TRANS_DDI_PVSYNC)
3845 flags |= DRM_MODE_FLAG_PVSYNC;
3846 else
3847 flags |= DRM_MODE_FLAG_NVSYNC;
3848
3849 pipe_config->base.adjusted_mode.flags |= flags;
3850
3851 switch (temp & TRANS_DDI_BPC_MASK) {
3852 case TRANS_DDI_BPC_6:
3853 pipe_config->pipe_bpp = 18;
3854 break;
3855 case TRANS_DDI_BPC_8:
3856 pipe_config->pipe_bpp = 24;
3857 break;
3858 case TRANS_DDI_BPC_10:
3859 pipe_config->pipe_bpp = 30;
3860 break;
3861 case TRANS_DDI_BPC_12:
3862 pipe_config->pipe_bpp = 36;
3863 break;
3864 default:
3865 break;
3866 }
3867
3868 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3869 case TRANS_DDI_MODE_SELECT_HDMI:
3870 pipe_config->has_hdmi_sink = true;
3871
3872 pipe_config->infoframes.enable |=
3873 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3874
3875 if (pipe_config->infoframes.enable)
3876 pipe_config->has_infoframe = true;
3877
3878 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3879 pipe_config->hdmi_scrambling = true;
3880 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3881 pipe_config->hdmi_high_tmds_clock_ratio = true;
3882 /* fall through */
3883 case TRANS_DDI_MODE_SELECT_DVI:
3884 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3885 pipe_config->lane_count = 4;
3886 break;
3887 case TRANS_DDI_MODE_SELECT_FDI:
3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3889 break;
3890 case TRANS_DDI_MODE_SELECT_DP_SST:
3891 if (encoder->type == INTEL_OUTPUT_EDP)
3892 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3893 else
3894 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3895 pipe_config->lane_count =
3896 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3897 intel_dp_get_m_n(intel_crtc, pipe_config);
3898
3899 if (INTEL_GEN(dev_priv) >= 11) {
3900 i915_reg_t dp_tp_ctl;
3901
3902 if (IS_GEN(dev_priv, 11))
3903 dp_tp_ctl = DP_TP_CTL(pipe_config->cpu_transcoder);
3904 else
> 3905 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
3906
3907 pipe_config->fec_enable =
3908 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3909
3910 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
3911 encoder->base.base.id, encoder->base.name,
3912 pipe_config->fec_enable);
3913 }
3914
3915 break;
3916 case TRANS_DDI_MODE_SELECT_DP_MST:
3917 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3918 pipe_config->lane_count =
3919 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3920 intel_dp_get_m_n(intel_crtc, pipe_config);
3921 break;
3922 default:
3923 break;
3924 }
3925
3926 pipe_config->has_audio =
3927 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3928
3929 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3930 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3931 /*
3932 * This is a big fat ugly hack.
3933 *
3934 * Some machines in UEFI boot mode provide us a VBT that has 18
3935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3936 * unknown we fail to light up. Yet the same BIOS boots up with
3937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3938 * max, not what it tells us to use.
3939 *
3940 * Note: This will still be broken if the eDP panel is not lit
3941 * up by the BIOS, and thus we can't get the mode at module
3942 * load.
3943 */
3944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3945 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3946 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3947 }
3948
3949 intel_ddi_clock_get(encoder, pipe_config);
3950
3951 if (IS_GEN9_LP(dev_priv))
3952 pipe_config->lane_lat_optim_mask =
3953 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3954
3955 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3956
3957 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3958
3959 intel_read_infoframe(encoder, pipe_config,
3960 HDMI_INFOFRAME_TYPE_AVI,
3961 &pipe_config->infoframes.avi);
3962 intel_read_infoframe(encoder, pipe_config,
3963 HDMI_INFOFRAME_TYPE_SPD,
3964 &pipe_config->infoframes.spd);
3965 intel_read_infoframe(encoder, pipe_config,
3966 HDMI_INFOFRAME_TYPE_VENDOR,
3967 &pipe_config->infoframes.hdmi);
3968 intel_read_infoframe(encoder, pipe_config,
3969 HDMI_INFOFRAME_TYPE_DRM,
3970 &pipe_config->infoframes.drm);
3971 }
3972
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 28068 bytes --]
next prev parent reply other threads:[~2019-09-23 14:22 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-20 11:42 [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2 Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 02/23] HAX drm/i915: Disable FEC entirely for now Maarten Lankhorst
2019-09-23 13:08 ` Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 03/23] drm/i915: Prepare to split crtc state in uapi and hw state Maarten Lankhorst
2019-09-24 23:40 ` Matt Roper
2019-09-25 9:09 ` Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 04/23] drm/i915: Handle a few more cases for hw/sw split Maarten Lankhorst
2019-09-24 23:40 ` Matt Roper
2019-09-20 11:42 ` [PATCH 05/23] drm/i915: Complete sw/hw split Maarten Lankhorst
2019-09-24 23:41 ` Matt Roper
2019-09-25 9:29 ` Maarten Lankhorst
2019-09-25 13:01 ` Ville Syrjälä
2019-09-25 14:12 ` Maarten Lankhorst
2019-09-25 14:18 ` Maarten Lankhorst
2019-09-25 14:54 ` Ville Syrjälä
2019-09-20 11:42 ` [PATCH 06/23] drm/i915: Get rid of crtc_state->fb_changed Maarten Lankhorst
2019-09-24 23:44 ` Matt Roper
2019-09-20 11:42 ` [PATCH 07/23] drm/i915: Remove begin/finish_crtc_commit Maarten Lankhorst
2019-09-25 4:17 ` Matt Roper
2019-09-25 14:14 ` Maarten Lankhorst
2019-09-25 22:14 ` Manasi Navare
2019-09-20 11:42 ` [PATCH 08/23] drm/i915: Rename planar linked plane variables Maarten Lankhorst
2019-09-25 4:30 ` Matt Roper
2019-09-20 11:42 ` [PATCH 09/23] drm/i915: Do not add all planes when checking scalers on glk+ Maarten Lankhorst
2019-09-25 4:55 ` Matt Roper
2019-09-25 12:45 ` Maarten Lankhorst
2019-09-25 13:02 ` Ville Syrjälä
2019-09-20 11:42 ` [PATCH 10/23] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid() Maarten Lankhorst
2019-09-25 5:30 ` Matt Roper
2019-09-25 5:56 ` Matt Roper
2019-09-25 22:09 ` Manasi Navare
2019-09-26 16:00 ` Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 11/23] drm/i915: Try to make bigjoiner work in atomic check Maarten Lankhorst
2019-09-26 3:48 ` Matt Roper
2019-09-30 14:12 ` Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 12/23] drm/i915: Enable big joiner support in enable and disable sequences Maarten Lankhorst
2019-09-26 5:18 ` Matt Roper
2019-09-26 23:54 ` Matt Roper
2019-09-27 8:25 ` Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 13/23] drm/i915: Make hardware readout work on i915 Maarten Lankhorst
2019-09-27 0:49 ` Matt Roper
2019-09-20 11:42 ` [PATCH 14/23] drm/i915: Prepare update_slave() for bigjoiner plane updates Maarten Lankhorst
2019-09-27 3:18 ` Matt Roper
2019-09-20 11:42 ` [PATCH 15/23] drm/i915: Link planes in a bigjoiner configuration Maarten Lankhorst
2019-10-01 16:44 ` Matt Roper
2019-10-01 17:21 ` Ville Syrjälä
2019-09-20 11:42 ` [PATCH 16/23] drm/i915: Program planes in bigjoiner mode Maarten Lankhorst
2019-09-26 13:06 ` Ville Syrjälä
2019-09-26 15:50 ` Maarten Lankhorst
2019-09-26 16:09 ` Ville Syrjälä
2019-09-26 16:13 ` Maarten Lankhorst
2019-09-26 16:26 ` Ville Syrjälä
2019-09-26 19:11 ` Ville Syrjälä
2019-09-27 8:56 ` Maarten Lankhorst
2019-09-27 14:41 ` Ville Syrjälä
2019-09-27 15:00 ` Ville Syrjälä
2019-09-20 11:42 ` [PATCH 17/23] drm/i915: Add intel_update_bigjoiner handling Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 18/23] drm/i915: Disable FBC in bigjoiner configuration Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 19/23] drm/i915: Prepare atomic plane check for bigjoiner planes Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 20/23] drm/i915: Make prepare_plane_fb() work with " Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 21/23] drm/i915: Make sure watermarks work correctly with bigjoiner as well Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 22/23] drm/i915: Add debugfs dumping for bigjoiner Maarten Lankhorst
2019-09-20 11:42 ` [PATCH 23/23] HAX to make it work on the icelake test system Maarten Lankhorst
2019-09-20 14:52 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2 Patchwork
2019-09-20 14:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-09-20 15:16 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-20 16:38 ` [Intel-gfx] [PATCH 01/23] " Ville Syrjälä
2019-09-23 12:52 ` [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3 Maarten Lankhorst
2019-09-23 13:03 ` Ville Syrjälä
2019-09-23 13:03 ` Ville Syrjälä
2019-09-23 14:49 ` [PATCH] drm/i915/dp: Fix dsc bpp calculations, v4 Maarten Lankhorst
2019-09-23 14:50 ` Maarten Lankhorst
2019-09-23 14:57 ` Ville Syrjälä
2019-09-23 15:56 ` Manasi Navare
2019-09-23 15:56 ` [Intel-gfx] " Ville Syrjälä
2019-09-23 14:22 ` kbuild test robot [this message]
2019-09-23 14:22 ` [Intel-gfx] [PATCH] drm/i915/dp: Fix dsc bpp calculations, v3 kbuild test robot
2019-09-23 15:53 ` Manasi Navare
2019-09-21 12:06 ` [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2 Sasha Levin
2019-09-21 15:22 ` ✗ Fi.CI.IGT: failure for series starting with [01/23] " Patchwork
2019-09-23 10:43 ` Maarten Lankhorst
2019-09-23 19:10 ` ✗ Fi.CI.BUILD: failure for series starting with drm/i915/dp: Fix dsc bpp calculations, v4. (rev3) Patchwork
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