[bug report] [media] rc: Introduce hix5hd2 IR transmitter driver

[bug report] [media] rc: Introduce hix5hd2 IR transmitter driver

[Dan Carpenter]

[ Ancient code, but maybe someone knows the answer.  - dan ]

Hello Guoxiong Yan,

The patch a84fcdaa9058: "[media] rc: Introduce hix5hd2 IR transmitter
driver" from Aug 30, 2014, leads to the following static checker
warning:

	./drivers/media/rc/ir-hix5hd2.c:112 (null)()
	warn: odd binop '0x3e80 & 0xffffffffffff0000'

drivers/media/rc/ir-hix5hd2.c
    95  static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
    96  {
    97          int timeout = 10000;
    98          u32 val, rate;
    99  
   100          writel_relaxed(0x01, priv->base + IR_ENABLE);
   101          while (readl_relaxed(priv->base + IR_BUSY)) {
   102                  if (timeout--) {
   103                          udelay(1);
   104                  } else {
   105                          dev_err(priv->dev, "IR_BUSY timeout\n");
   106                          return -ETIMEDOUT;
   107                  }
   108          }
   109  
   110          /* Now only support raw mode, with symbol start from low to high */
   111          rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
   112          val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is zero because << has higher precedence than &.  But maybe what
was intended was:

		val = (IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK) << IR_CFG_WIDTH_SHIFT;

   113          val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
                       ^^^^^^^^^^^^^^^^^
This is zero anyway, so it doesn't matter but maybe there is a precedence
bug here as well.

   114          val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
   115                 << IR_CFG_INT_LEVEL_SHIFT;
                       ^^^^^^^^^^^^^^^^^^^^^^^^^
Same

   116          val |= IR_CFG_MODE_RAW;
   117          val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Same

   118          writel_relaxed(val, priv->base + IR_CONFIG);
   119  
   120          writel_relaxed(0x00, priv->base + IR_INTM);
   121          /* write arbitrary value to start  */
   122          writel_relaxed(0x01, priv->base + IR_START);
   123          return 0;
   124  }

regards,
dan carpenter