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From: kholk11@gmail.com
To: linux-arm-msm@vger.kernel.org
Cc: kholk11@gmail.com, iommu@lists.linux-foundation.org,
	marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com,
	joro@8bytes.org
Subject: [PATCH v4 3/7] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
Date: Wed,  2 Oct 2019 00:02:01 +0200	[thread overview]
Message-ID: <20191001220205.6423-4-kholk11@gmail.com> (raw)
In-Reply-To: <20191001220205.6423-1-kholk11@gmail.com>

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

As also stated in the arm-smmu driver, we must write the TCR before
writing the TTBRs, since the TCR determines the access behavior of
some fields.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 drivers/iommu/qcom_iommu.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 504ca69adc5a..c8957ec83b92 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -267,6 +267,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 			ctx->secure_init = true;
 		}
 
+		/* TCR */
+		iommu_writel(ctx, ARM_SMMU_CB_TCR2,
+				(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
+				FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
+		iommu_writel(ctx, ARM_SMMU_CB_TCR,
+				pgtbl_cfg.arm_lpae_s1_cfg.tcr);
+
 		/* TTBRs */
 		iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
 				pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
@@ -275,13 +282,6 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 				pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
 				FIELD_PREP(TTBRn_ASID, ctx->asid));
 
-		/* TCR */
-		iommu_writel(ctx, ARM_SMMU_CB_TCR2,
-				(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
-				FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
-		iommu_writel(ctx, ARM_SMMU_CB_TCR,
-				pgtbl_cfg.arm_lpae_s1_cfg.tcr);
-
 		/* MAIRs (stage-1 only) */
 		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
 				pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
-- 
2.21.0


WARNING: multiple messages have this Message-ID (diff)
From: kholk11@gmail.com
To: linux-arm-msm@vger.kernel.org
Cc: marijns95@gmail.com, iommu@lists.linux-foundation.org,
	agross@kernel.org, kholk11@gmail.com
Subject: [PATCH v4 3/7] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
Date: Wed,  2 Oct 2019 00:02:01 +0200	[thread overview]
Message-ID: <20191001220205.6423-4-kholk11@gmail.com> (raw)
In-Reply-To: <20191001220205.6423-1-kholk11@gmail.com>

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

As also stated in the arm-smmu driver, we must write the TCR before
writing the TTBRs, since the TCR determines the access behavior of
some fields.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
 drivers/iommu/qcom_iommu.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 504ca69adc5a..c8957ec83b92 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -267,6 +267,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 			ctx->secure_init = true;
 		}
 
+		/* TCR */
+		iommu_writel(ctx, ARM_SMMU_CB_TCR2,
+				(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
+				FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
+		iommu_writel(ctx, ARM_SMMU_CB_TCR,
+				pgtbl_cfg.arm_lpae_s1_cfg.tcr);
+
 		/* TTBRs */
 		iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
 				pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
@@ -275,13 +282,6 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 				pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
 				FIELD_PREP(TTBRn_ASID, ctx->asid));
 
-		/* TCR */
-		iommu_writel(ctx, ARM_SMMU_CB_TCR2,
-				(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
-				FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
-		iommu_writel(ctx, ARM_SMMU_CB_TCR,
-				pgtbl_cfg.arm_lpae_s1_cfg.tcr);
-
 		/* MAIRs (stage-1 only) */
 		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
 				pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
-- 
2.21.0

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  parent reply	other threads:[~2019-10-01 22:02 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-01 22:01 [PATCH v4 0/7] Add support for QCOM IOMMU v2 and 500 kholk11
2019-10-01 22:01 ` kholk11
2019-10-01 22:01 ` [PATCH v4 1/7] firmware: qcom: scm: Add function to set IOMMU pagetable addressing kholk11
2019-10-01 22:01   ` kholk11
2019-10-15 11:14   ` Joerg Roedel
2019-10-15 11:14     ` Joerg Roedel
2019-10-15 12:33     ` AngeloGioacchino Del Regno
2019-10-15 12:33       ` AngeloGioacchino Del Regno
2019-10-15 12:40       ` Joerg Roedel
2019-10-15 12:40         ` Joerg Roedel
2019-10-15 13:09         ` AngeloGioacchino Del Regno
2019-10-15 13:09           ` AngeloGioacchino Del Regno
2019-10-01 22:02 ` [PATCH v4 2/7] iommu/qcom: Use the asid read from device-tree if specified kholk11
2019-10-01 22:02   ` kholk11
2019-10-15 12:09   ` Robin Murphy
2019-10-15 12:09     ` Robin Murphy
2019-10-15 13:06     ` AngeloGioacchino Del Regno
2019-10-15 13:06       ` AngeloGioacchino Del Regno
2019-10-01 22:02 ` kholk11 [this message]
2019-10-01 22:02   ` [PATCH v4 3/7] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior kholk11
2019-10-01 22:02 ` [PATCH v4 4/7] iommu/qcom: Properly reset the IOMMU context kholk11
2019-10-01 22:02   ` kholk11
2019-10-02 11:29   ` Robin Murphy
2019-10-02 11:29     ` Robin Murphy
2019-10-01 22:02 ` [PATCH v4 5/7] iommu/qcom: Add support for AArch64 IOMMU pagetables kholk11
2019-10-01 22:02   ` kholk11
2019-10-01 22:02 ` [PATCH v4 6/7] iommu/qcom: Index contexts by asid number to allow asid 0 kholk11
2019-10-01 22:02   ` kholk11
2019-10-01 22:02 ` [PATCH v4 7/7] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts kholk11
2019-10-01 22:02   ` kholk11
2019-10-05  4:56 ` [PATCH v4 0/7] Add support for QCOM IOMMU v2 and 500 Bjorn Andersson
2019-10-05  4:56   ` Bjorn Andersson
2019-10-05  9:32   ` AngeloGioacchino Del Regno
2019-10-05  9:32     ` AngeloGioacchino Del Regno

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