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From: Marc Zyngier <maz@kernel.org>
To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>,
	uohanjun@huawei.com, huawei.libin@huawei.com,
	liwei391@huawei.com,
	Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v3 2/2] arm64: Document ICC_CTLR_EL3.PMHE setting requirements
Date: Wed,  2 Oct 2019 10:06:13 +0100	[thread overview]
Message-ID: <20191002090613.14236-3-maz@kernel.org> (raw)
In-Reply-To: <20191002090613.14236-1-maz@kernel.org>

It goes without saying, but better saying it: the kernel expects
ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and
for that setting not to change during the lifetime of the kernel.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 Documentation/arm64/booting.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index d3f3a60fbf25..5d78a6f5b0ae 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -213,6 +213,9 @@ Before jumping into the kernel, the following conditions must be met:
 
       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
+      - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
+        all CPUs the kernel is executing on, and must stay constant
+        for the lifetime of the kernel.
 
   - If the kernel is entered at EL1:
 
-- 
2.20.1


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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	huawei.libin@huawei.com, uohanjun@huawei.com,
	liwei391@huawei.com, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v3 2/2] arm64: Document ICC_CTLR_EL3.PMHE setting requirements
Date: Wed,  2 Oct 2019 10:06:13 +0100	[thread overview]
Message-ID: <20191002090613.14236-3-maz@kernel.org> (raw)
In-Reply-To: <20191002090613.14236-1-maz@kernel.org>

It goes without saying, but better saying it: the kernel expects
ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and
for that setting not to change during the lifetime of the kernel.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 Documentation/arm64/booting.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index d3f3a60fbf25..5d78a6f5b0ae 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -213,6 +213,9 @@ Before jumping into the kernel, the following conditions must be met:
 
       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
+      - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
+        all CPUs the kernel is executing on, and must stay constant
+        for the lifetime of the kernel.
 
   - If the kernel is entered at EL1:
 
-- 
2.20.1


  parent reply	other threads:[~2019-10-02  9:20 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-02  9:06 [PATCH v3 0/2] arm64: Relax ICC_PMR_EL1 synchronisation when possible Marc Zyngier
2019-10-02  9:06 ` Marc Zyngier
2019-10-02  9:06 ` [PATCH v3 1/2] arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear Marc Zyngier
2019-10-02  9:06   ` Marc Zyngier
2019-10-23  8:38   ` liwei (GF)
2019-10-23  8:38     ` liwei (GF)
2019-10-23 12:13     ` Marc Zyngier
2019-10-23 12:13       ` Marc Zyngier
2019-10-26  1:42       ` liwei (GF)
2019-10-26  1:42         ` liwei (GF)
2019-10-02  9:06 ` Marc Zyngier [this message]
2019-10-02  9:06   ` [PATCH v3 2/2] arm64: Document ICC_CTLR_EL3.PMHE setting requirements Marc Zyngier
2019-10-15 17:30 ` [PATCH v3 0/2] arm64: Relax ICC_PMR_EL1 synchronisation when possible Catalin Marinas
2019-10-15 17:30   ` Catalin Marinas

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