* [PATCH V2 1/4] clk: tegra: mark fuse clock as critical
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
For a little over a year, U-Boot on Tegra124 has configured the flow
controller to perform automatic RAM re-repair on off->on power transitions
of the CPU rail1]. This is mandatory for correct operation of Tegra124.
However, RAM re-repair relies on certain clocks, which the kernel must
enable and leave running. The fuse clock is one of those clocks. Mark this
clock as critical so that LP1 power mode (system suspend) operates
correctly.
[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: Set CRITICAL flag on the clock, rather than enabling it in
tegra124_init_table[].
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 1ed85f120a1b..76dd91eebd13 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
- GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
+ GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V2 1/4] clk: tegra: mark fuse clock as critical
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
For a little over a year, U-Boot on Tegra124 has configured the flow
controller to perform automatic RAM re-repair on off->on power transitions
of the CPU rail1]. This is mandatory for correct operation of Tegra124.
However, RAM re-repair relies on certain clocks, which the kernel must
enable and leave running. The fuse clock is one of those clocks. Mark this
clock as critical so that LP1 power mode (system suspend) operates
correctly.
[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: Set CRITICAL flag on the clock, rather than enabling it in
tegra124_init_table[].
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 1ed85f120a1b..76dd91eebd13 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
- GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
+ GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH V2 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1
2019-10-03 20:18 ` Stephen Warren
(?)
@ 2019-10-03 20:18 ` Stephen Warren
-1 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Michael Turquette, Stephen Boyd, linux-arm-kernel, linux-tegra,
linux-clk
From: Stephen Warren <swarren@nvidia.com>
For a little over a year, U-Boot has configured the flow controller to
perform automatic RAM re-repair on off->on power transitions of the CPU
rail1]. This is mandatory for correct operation of Tegra124. However, RAM
re-repair relies on certain clocks, which the kernel must enable and
leave running. PLLP is one of those clocks. This clock is shut down
during LP1 in order to save power. Enable bypass (which I believe routes
osc_div_clk, essentially the crystal clock, to the PLL output) so that
this clock signal toggles even though the PLL is not active. This is
required so that LP1 power mode (system suspend) operates correctly.
The bypass configuration must then be undone when resuming from LP1, so
that all peripheral clocks run at the expected rate. Without this, many
peripherals won't work correctly; for example, the UART baud rate would
be incorrect.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
downstream code makes this change conditional upon the active CPU
cluster. The upstream kernel currently doesn't support cluster switching,
so this patch doesn't test the active CPU cluster ID.
[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index b408fa56eb89..6922dd8d3e2d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -370,6 +370,14 @@ _pll_m_c_x_done:
pll_locked r1, r0, CLK_RESET_PLLC_BASE
pll_locked r1, r0, CLK_RESET_PLLX_BASE
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
+ beq 1f
+ ldr r1, [r0, #CLK_RESET_PLLP_BASE]
+ bic r1, r1, #(1<<31) @ disable PllP bypass
+ str r1, [r0, #CLK_RESET_PLLP_BASE]
+1:
+
mov32 r7, TEGRA_TMRUS_BASE
ldr r1, [r7]
add r1, r1, #LOCK_DELAY
@@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k:
str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
/* disable PLLP, PLLA, PLLC and PLLX */
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
ldr r0, [r5, #CLK_RESET_PLLP_BASE]
+ orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
For a little over a year, U-Boot has configured the flow controller to
perform automatic RAM re-repair on off->on power transitions of the CPU
rail1]. This is mandatory for correct operation of Tegra124. However, RAM
re-repair relies on certain clocks, which the kernel must enable and
leave running. PLLP is one of those clocks. This clock is shut down
during LP1 in order to save power. Enable bypass (which I believe routes
osc_div_clk, essentially the crystal clock, to the PLL output) so that
this clock signal toggles even though the PLL is not active. This is
required so that LP1 power mode (system suspend) operates correctly.
The bypass configuration must then be undone when resuming from LP1, so
that all peripheral clocks run at the expected rate. Without this, many
peripherals won't work correctly; for example, the UART baud rate would
be incorrect.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
downstream code makes this change conditional upon the active CPU
cluster. The upstream kernel currently doesn't support cluster switching,
so this patch doesn't test the active CPU cluster ID.
[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index b408fa56eb89..6922dd8d3e2d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -370,6 +370,14 @@ _pll_m_c_x_done:
pll_locked r1, r0, CLK_RESET_PLLC_BASE
pll_locked r1, r0, CLK_RESET_PLLX_BASE
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
+ beq 1f
+ ldr r1, [r0, #CLK_RESET_PLLP_BASE]
+ bic r1, r1, #(1<<31) @ disable PllP bypass
+ str r1, [r0, #CLK_RESET_PLLP_BASE]
+1:
+
mov32 r7, TEGRA_TMRUS_BASE
ldr r1, [r7]
add r1, r1, #LOCK_DELAY
@@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k:
str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
/* disable PLLP, PLLA, PLLC and PLLX */
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
ldr r0, [r5, #CLK_RESET_PLLP_BASE]
+ orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
For a little over a year, U-Boot has configured the flow controller to
perform automatic RAM re-repair on off->on power transitions of the CPU
rail1]. This is mandatory for correct operation of Tegra124. However, RAM
re-repair relies on certain clocks, which the kernel must enable and
leave running. PLLP is one of those clocks. This clock is shut down
during LP1 in order to save power. Enable bypass (which I believe routes
osc_div_clk, essentially the crystal clock, to the PLL output) so that
this clock signal toggles even though the PLL is not active. This is
required so that LP1 power mode (system suspend) operates correctly.
The bypass configuration must then be undone when resuming from LP1, so
that all peripheral clocks run at the expected rate. Without this, many
peripherals won't work correctly; for example, the UART baud rate would
be incorrect.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
downstream code makes this change conditional upon the active CPU
cluster. The upstream kernel currently doesn't support cluster switching,
so this patch doesn't test the active CPU cluster ID.
[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index b408fa56eb89..6922dd8d3e2d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -370,6 +370,14 @@ _pll_m_c_x_done:
pll_locked r1, r0, CLK_RESET_PLLC_BASE
pll_locked r1, r0, CLK_RESET_PLLX_BASE
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
+ beq 1f
+ ldr r1, [r0, #CLK_RESET_PLLP_BASE]
+ bic r1, r1, #(1<<31) @ disable PllP bypass
+ str r1, [r0, #CLK_RESET_PLLP_BASE]
+1:
+
mov32 r7, TEGRA_TMRUS_BASE
ldr r1, [r7]
add r1, r1, #LOCK_DELAY
@@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k:
str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
/* disable PLLP, PLLA, PLLC and PLLX */
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+ cmp r1, #TEGRA30
ldr r0, [r5, #CLK_RESET_PLLP_BASE]
+ orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 3/4] ARM: tegra: modify reshift divider during LP1
2019-10-03 20:18 ` Stephen Warren
(?)
@ 2019-10-03 20:18 ` Stephen Warren
-1 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Michael Turquette, Stephen Boyd, linux-arm-kernel, linux-tegra,
linux-clk
From: Stephen Warren <swarren@nvidia.com>
The reshift hardware module implements the RAM re-repair process. This
module uses PLLP as an input clock during LP1 resume. The input divider
for this clock is typically set for PLLP's normal rate. During LP1
resume, PLLP is bypassed and so runs at the crystal rate, which is much
slower. Consequently, decrease the divider so that the reshift module
runs at a reasonable rate during LP1 resume.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6922dd8d3e2d..6191f9456288 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -59,6 +59,9 @@
#define CLK_RESET_PLLX_MISC3_IDDQ 3
#define CLK_RESET_PLLM_MISC_IDDQ 5
#define CLK_RESET_PLLC_MISC_IDDQ 26
+#define CLK_RESET_PLLP_RESHIFT 0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
@@ -373,9 +376,13 @@ _pll_m_c_x_done:
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
+
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
+
+ mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+ str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
1:
mov32 r7, TEGRA_TMRUS_BASE
@@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k:
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
+ beq 1f
+ mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+ str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+1:
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 3/4] ARM: tegra: modify reshift divider during LP1
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
The reshift hardware module implements the RAM re-repair process. This
module uses PLLP as an input clock during LP1 resume. The input divider
for this clock is typically set for PLLP's normal rate. During LP1
resume, PLLP is bypassed and so runs at the crystal rate, which is much
slower. Consequently, decrease the divider so that the reshift module
runs at a reasonable rate during LP1 resume.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6922dd8d3e2d..6191f9456288 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -59,6 +59,9 @@
#define CLK_RESET_PLLX_MISC3_IDDQ 3
#define CLK_RESET_PLLM_MISC_IDDQ 5
#define CLK_RESET_PLLC_MISC_IDDQ 26
+#define CLK_RESET_PLLP_RESHIFT 0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
@@ -373,9 +376,13 @@ _pll_m_c_x_done:
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
+
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
+
+ mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+ str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
1:
mov32 r7, TEGRA_TMRUS_BASE
@@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k:
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
+ beq 1f
+ mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+ str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+1:
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 3/4] ARM: tegra: modify reshift divider during LP1
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
The reshift hardware module implements the RAM re-repair process. This
module uses PLLP as an input clock during LP1 resume. The input divider
for this clock is typically set for PLLP's normal rate. During LP1
resume, PLLP is bypassed and so runs at the crystal rate, which is much
slower. Consequently, decrease the divider so that the reshift module
runs at a reasonable rate during LP1 resume.
NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6922dd8d3e2d..6191f9456288 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -59,6 +59,9 @@
#define CLK_RESET_PLLX_MISC3_IDDQ 3
#define CLK_RESET_PLLM_MISC_IDDQ 5
#define CLK_RESET_PLLC_MISC_IDDQ 26
+#define CLK_RESET_PLLP_RESHIFT 0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
@@ -373,9 +376,13 @@ _pll_m_c_x_done:
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
+
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
+
+ mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+ str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
1:
mov32 r7, TEGRA_TMRUS_BASE
@@ -644,6 +651,10 @@ tegra30_switch_cpu_to_clk32k:
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
+ beq 1f
+ mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+ str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+1:
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLA_BASE]
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 4/4] ARM: tegra: use clk_m CPU on Tegra124 LP1 resume
2019-10-03 20:18 ` Stephen Warren
(?)
@ 2019-10-03 20:18 ` Stephen Warren
-1 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Michael Turquette, Stephen Boyd, linux-arm-kernel, linux-tegra,
linux-clk
From: Stephen Warren <swarren@nvidia.com>
Configure the clock controller to set an alternate clock for the CPU when
it receives an IRQ during LP1 (system suspend). Specifically, use clk_m
(the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the
LP1 wake event. This reduces the amount of time taken to resume from LP1.
NVIDIA's downstream kernel executes this code on both Tegra30 and
Tegra124, so it appears OK to make this change unconditionally.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6191f9456288..ba5e9c07d1b6 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k:
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
_no_pll_in_iddq:
- /* switch to CLKS */
- mov r0, #0 /* brust policy = 32KHz */
+ /*
+ * Switch to clk_s (32KHz); bits 28:31=0
+ * Enable burst on CPU IRQ; bit 24=1
+ * Set IRQ burst clock source to clk_m; bits 10:8=0
+ */
+ mov r0, #(1 << 24)
str r0, [r5, #CLK_RESET_SCLK_BURST]
ret lr
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 4/4] ARM: tegra: use clk_m CPU on Tegra124 LP1 resume
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Configure the clock controller to set an alternate clock for the CPU when
it receives an IRQ during LP1 (system suspend). Specifically, use clk_m
(the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the
LP1 wake event. This reduces the amount of time taken to resume from LP1.
NVIDIA's downstream kernel executes this code on both Tegra30 and
Tegra124, so it appears OK to make this change unconditionally.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6191f9456288..ba5e9c07d1b6 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k:
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
_no_pll_in_iddq:
- /* switch to CLKS */
- mov r0, #0 /* brust policy = 32KHz */
+ /*
+ * Switch to clk_s (32KHz); bits 28:31=0
+ * Enable burst on CPU IRQ; bit 24=1
+ * Set IRQ burst clock source to clk_m; bits 10:8=0
+ */
+ mov r0, #(1 << 24)
str r0, [r5, #CLK_RESET_SCLK_BURST]
ret lr
--
2.23.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V2 4/4] ARM: tegra: use clk_m CPU on Tegra124 LP1 resume
@ 2019-10-03 20:18 ` Stephen Warren
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Warren @ 2019-10-03 20:18 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad
Cc: Stephen Boyd, linux-tegra, Michael Turquette, linux-clk,
linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Configure the clock controller to set an alternate clock for the CPU when
it receives an IRQ during LP1 (system suspend). Specifically, use clk_m
(the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the
LP1 wake event. This reduces the amount of time taken to resume from LP1.
NVIDIA's downstream kernel executes this code on both Tegra30 and
Tegra124, so it appears OK to make this change unconditionally.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: No change.
---
arch/arm/mach-tegra/sleep-tegra30.S | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6191f9456288..ba5e9c07d1b6 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k:
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
_no_pll_in_iddq:
- /* switch to CLKS */
- mov r0, #0 /* brust policy = 32KHz */
+ /*
+ * Switch to clk_s (32KHz); bits 28:31=0
+ * Enable burst on CPU IRQ; bit 24=1
+ * Set IRQ burst clock source to clk_m; bits 10:8=0
+ */
+ mov r0, #(1 << 24)
str r0, [r5, #CLK_RESET_SCLK_BURST]
ret lr
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH V2 1/4] clk: tegra: mark fuse clock as critical
2019-10-03 20:18 ` Stephen Warren
(?)
@ 2019-10-03 20:26 ` Stephen Boyd
-1 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-03 20:26 UTC (permalink / raw)
To: Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Warren, Thierry Reding
Cc: Michael Turquette, linux-arm-kernel, linux-tegra, linux-clk
Quoting Stephen Warren (2019-10-03 13:18:34)
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index 1ed85f120a1b..76dd91eebd13 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = {
> GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
> GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
> GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
> - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
> + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
Please comment in the code why it's critical so we don't have to dig
through commit history to figure this out.
> GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
> GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
> GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH V2 1/4] clk: tegra: mark fuse clock as critical
@ 2019-10-03 20:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-03 20:26 UTC (permalink / raw)
To: Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Warren, Thierry Reding
Cc: linux-tegra, Michael Turquette, linux-clk, linux-arm-kernel
Quoting Stephen Warren (2019-10-03 13:18:34)
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index 1ed85f120a1b..76dd91eebd13 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = {
> GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
> GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
> GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
> - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
> + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
Please comment in the code why it's critical so we don't have to dig
through commit history to figure this out.
> GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
> GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
> GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH V2 1/4] clk: tegra: mark fuse clock as critical
@ 2019-10-03 20:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-03 20:26 UTC (permalink / raw)
To: Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Warren, Thierry Reding
Cc: linux-tegra, Michael Turquette, linux-clk, linux-arm-kernel
Quoting Stephen Warren (2019-10-03 13:18:34)
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index 1ed85f120a1b..76dd91eebd13 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -785,7 +785,7 @@ static struct tegra_periph_init_data gate_clks[] = {
> GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
> GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
> GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
> - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
> + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
Please comment in the code why it's critical so we don't have to dig
through commit history to figure this out.
> GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
> GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
> GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
^ permalink raw reply [flat|nested] 15+ messages in thread