From: Peter Zijlstra <peterz@infradead.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>,
Sebastian Andrzej Siewior <sebastian@breakpoint.cc>,
Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>,
Will Deacon <will@kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM
Date: Wed, 9 Oct 2019 10:46:10 +0200 [thread overview]
Message-ID: <20191009084610.GG2311@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <CAK8P3a0UH8_pSPbEd7fRjws-TZ=+q-gLQZXvEOtoX9YtZY9tmA@mail.gmail.com>
On Tue, Oct 08, 2019 at 04:32:27PM +0200, Arnd Bergmann wrote:
> diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> index 8b701f8e175c..6bf4964c105c 100644
> --- a/arch/arm/include/asm/cmpxchg.h
> +++ b/arch/arm/include/asm/cmpxchg.h
> @@ -114,6 +114,24 @@ static inline unsigned long __xchg(unsigned long
> x, volatile void *ptr, int size
> return ret;
> }
>
> +#ifdef CONFIG_CPU_V6
> +static inline unsigned short smp_xchg16_relaxed(volatile unsigned
> short *ptr, unsigned short x)
> +{
> + unsigned short ret, tmp;
> + asm volatile("@ smp_xchg16_relaxed\n"
> + ".arch armv6k\n"
> + "1: ldrexh %0, [%3]\n"
> + " strexh %1, %2, [%3]\n"
> + " teq %1, #0\n"
> + " bne 1b"
> + : "=&r" (ret), "=&r" (tmp)
> + : "r" (x), "r" (ptr)
> + : "memory", "cc");
> + return ret;
> +}
> +#define smp_xchg16_relaxed smp_xchg16_relaxed
> +#endif
Why is this not in __xchg() as a variant for case 2 ?
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next prev parent reply other threads:[~2019-10-09 8:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-07 21:44 [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 1/3] ARM: Use qrwlock implementation Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 2/3] ARM: Use qspinlock implementation Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 3/3] ARM: Inline locking functions for !PREEMPTION Sebastian Andrzej Siewior
2019-10-08 11:42 ` [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Arnd Bergmann
2019-10-08 13:36 ` Waiman Long
2019-10-08 14:32 ` Arnd Bergmann
2019-10-08 19:47 ` Sebastian Andrzej Siewior
2019-10-08 21:47 ` Arnd Bergmann
2019-10-08 22:02 ` Sebastian Andrzej Siewior
2019-10-09 8:15 ` Arnd Bergmann
2019-10-09 8:46 ` Peter Zijlstra [this message]
2019-10-09 8:57 ` Arnd Bergmann
2019-10-09 9:31 ` Peter Zijlstra
2019-10-09 10:31 ` Arnd Bergmann
2019-10-09 10:56 ` Peter Zijlstra
2019-10-09 12:00 ` Arnd Bergmann
2019-10-09 12:06 ` Peter Zijlstra
2019-10-09 12:52 ` Will Deacon
2019-10-09 13:50 ` Arnd Bergmann
2019-10-09 21:42 ` Sebastian Andrzej Siewior
2019-10-08 19:32 ` Sebastian Andrzej Siewior
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