From: Peter Zijlstra <peterz@infradead.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>,
Sebastian Andrzej Siewior <sebastian@breakpoint.cc>,
Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>,
Will Deacon <will@kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM
Date: Wed, 9 Oct 2019 14:06:39 +0200 [thread overview]
Message-ID: <20191009120639.GI2311@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <CAK8P3a1CyaqHvx+UC+ZeJYDjU4x52hQ9sKyEMiOc=dKq8NTYKg@mail.gmail.com>
On Wed, Oct 09, 2019 at 02:00:05PM +0200, Arnd Bergmann wrote:
> On Wed, Oct 9, 2019 at 12:57 PM Peter Zijlstra <peterz@infradead.org> wrote:
> > On Wed, Oct 09, 2019 at 12:31:24PM +0200, Arnd Bergmann wrote:
> > > On Wed, Oct 9, 2019 at 11:31 AM Peter Zijlstra <peterz@infradead.org> wrote:
> > > I assume the 16-bit xchg_relaxed() in qspinlock.c was meant as
> > > an optimization for x86 and other cmpxchg based architectures but
> > > doesn't actually help on ll/sc based architectures that get the
> > > reservation on the whole cache line anyway?
> >
> > It does actually help here too, because it allows other operations to be
> > regular load/stores.
> >
> > Look at the #if _Q_PENDING_BITS==8 in qspinlock.c, as opposed to the
> > #else where they're all atomic_*().
>
> Oh, is that safe with an xchg() implementation that operates on the whole
> 32 bit when a concurrent thread can do a simple store to one half of it?
It had better be, otherwise LL/SC'd be broken. SC _must_ fail when there
is a contending store.
> The ARM architecture reference says "It is UNPREDICTABLE whether the
> transition from Exclusive Access to Open Access state occurs when the
> Store or StoreExcl is from another observer.", which sounds to me
> me like the xchg_small() trick would not work with the qspinlock
> implementation on ARM. [I see that mips, openrisc and xtensa do this,
> but did not try to find out whether they have ll/sc semantics that make
> it safe when another thread does a plain store to the reservation]
Will?
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next prev parent reply other threads:[~2019-10-09 12:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-07 21:44 [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 1/3] ARM: Use qrwlock implementation Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 2/3] ARM: Use qspinlock implementation Sebastian Andrzej Siewior
2019-10-07 21:44 ` [PATCH 3/3] ARM: Inline locking functions for !PREEMPTION Sebastian Andrzej Siewior
2019-10-08 11:42 ` [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Arnd Bergmann
2019-10-08 13:36 ` Waiman Long
2019-10-08 14:32 ` Arnd Bergmann
2019-10-08 19:47 ` Sebastian Andrzej Siewior
2019-10-08 21:47 ` Arnd Bergmann
2019-10-08 22:02 ` Sebastian Andrzej Siewior
2019-10-09 8:15 ` Arnd Bergmann
2019-10-09 8:46 ` Peter Zijlstra
2019-10-09 8:57 ` Arnd Bergmann
2019-10-09 9:31 ` Peter Zijlstra
2019-10-09 10:31 ` Arnd Bergmann
2019-10-09 10:56 ` Peter Zijlstra
2019-10-09 12:00 ` Arnd Bergmann
2019-10-09 12:06 ` Peter Zijlstra [this message]
2019-10-09 12:52 ` Will Deacon
2019-10-09 13:50 ` Arnd Bergmann
2019-10-09 21:42 ` Sebastian Andrzej Siewior
2019-10-08 19:32 ` Sebastian Andrzej Siewior
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