[PATCH] drm/i915: Move L3 MOCS to engine reset domain.

* [PATCH] drm/i915: Move L3 MOCS to engine reset domain.
@ 2019-10-16  4:05 Prathap Kumar Valsan
  2019-10-16  4:22 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Prathap Kumar Valsan @ 2019-10-16  4:05 UTC (permalink / raw)
  To: intel-gfx

Gen12 has L3 MOCS in engine reset domain, having us to re-initialize on
an engine reset.

References: https://bugs.freedesktop.org/show_bug.cgi?id=111723
References: https://bugs.freedesktop.org/show_bug.cgi?id=111645
References: HSDES#1607983814
References: HSDES#14010115701

Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 728704bbbe18..774c5df0d0e9 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -365,6 +365,8 @@ static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 	return table->table[I915_MOCS_PTE].control_value;
 }
 
+static void intel_mocs_init_l3cc_table(struct intel_gt *gt);
+
 /**
  * intel_mocs_init_engine() - emit the mocs control table
  * @engine:	The engine for whom to emit the registers.
@@ -380,6 +382,9 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 	unsigned int index;
 	u32 unused_value;
 
+	if (IS_GEN(gt->i915, 12) && engine->class == RENDER_CLASS)
+		intel_mocs_init_l3cc_table(gt);
+
 	/* Platforms with global MOCS do not need per-engine initialization. */
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
 		return;
-- 
2.20.1

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