Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150

[Stephen Boyd <sboyd@kernel.org>]

Quoting Vinod Koul (2019-10-16 05:23:43)
> Hi Steve,
> 
> Looks like I missed replying to this one, apologies!
> 
> On 17-09-19, 09:09, Stephen Boyd wrote:
> > Quoting Vinod Koul (2019-09-17 02:16:23)
> > > The initial upstreaming of SM8150 GCC driver missed few clock so add
> > > them up now.
> > > 
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > 
> > Should have some sort of fixes tag?
> 
> Not really, the drivers to use these clks are not upstream so we dont
> miss it yet

Ok.

> 
> > 
> > >  drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++
> > >  1 file changed, 172 insertions(+)
> > > 
> > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > index 12ca2d14797f..13d4d14a5744 100644
> > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> > >         },
> > >  };
> > >  
> > > +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> > > +       .halt_check = BRANCH_HALT_SKIP,
> > 
> > Why skip?
> 
> I will explore and add comments for that
> 
> > > +       .clkr = {
> > > +               .enable_reg = 0x52004,
> > > +               .enable_mask = BIT(15),
> > > +               .hw.init = &(struct clk_init_data){
> > > +                       .name = "gcc_gpu_gpll0_clk_src",
> > > +                       .parent_hws = (const struct clk_hw *[]){
> > > +                               &gpll0.clkr.hw },
> > > +                       .num_parents = 1,
> > > +                       .flags = CLK_SET_RATE_PARENT,
> > > +                       .ops = &clk_branch2_ops,
> > > +               },
> > > +       },
> > > +};
> > > +
> > > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> > > +       .halt_check = BRANCH_HALT_SKIP,
> > 
> > Why skip?
> > 

Any answer from the explorations?