From: Christoph Hellwig <hch@lst.de>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Christoph Hellwig <hch@lst.de>
Subject: Re: RISC-V nommu support v5
Date: Fri, 18 Oct 2019 17:25:20 +0200 [thread overview]
Message-ID: <20191018152520.GA32281@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1910172029170.3156@viisi.sifive.com>
On Thu, Oct 17, 2019 at 08:29:59PM -0700, Paul Walmsley wrote:
> On Fri, 18 Oct 2019, Anup Patel wrote:
>
> > It will be really cool to have this series for Linux-5.4-rcX.
>
> It's way too big to go in via the -rc series. I'm hoping to have it ready
> to go for v5.5-rc1.
Yes, this is 5.5 material. Btw, the buildbot found two issues that
require one liner fixes, so I'll resend again this weekend.
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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@sifive.com>,
Christoph Hellwig <hch@lst.de>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>
Subject: Re: RISC-V nommu support v5
Date: Fri, 18 Oct 2019 17:25:20 +0200 [thread overview]
Message-ID: <20191018152520.GA32281@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1910172029170.3156@viisi.sifive.com>
On Thu, Oct 17, 2019 at 08:29:59PM -0700, Paul Walmsley wrote:
> On Fri, 18 Oct 2019, Anup Patel wrote:
>
> > It will be really cool to have this series for Linux-5.4-rcX.
>
> It's way too big to go in via the -rc series. I'm hoping to have it ready
> to go for v5.5-rc1.
Yes, this is 5.5 material. Btw, the buildbot found two issues that
require one liner fixes, so I'll resend again this weekend.
next prev parent reply other threads:[~2019-10-18 15:25 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 01/15] riscv: cleanup <asm/bug.h> Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:50 ` Anup Patel
2019-10-18 2:50 ` Anup Patel
2019-10-23 22:04 ` Paul Walmsley
2019-10-23 22:04 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 02/15] riscv: cleanup do_trap_break Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:51 ` Anup Patel
2019-10-18 2:51 ` Anup Patel
2019-10-23 22:05 ` Paul Walmsley
2019-10-23 22:05 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 03/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:51 ` Anup Patel
2019-10-18 2:51 ` Anup Patel
2019-10-18 23:55 ` Paul Walmsley
2019-10-18 23:55 ` Paul Walmsley
2019-10-28 8:12 ` Christoph Hellwig
2019-10-28 8:12 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 04/15] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:52 ` Anup Patel
2019-10-18 2:52 ` Anup Patel
2019-10-17 17:37 ` [PATCH 05/15] riscv: poison SBI calls " Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 06/15] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 07/15] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:55 ` Anup Patel
2019-10-18 2:55 ` Anup Patel
2019-10-17 17:37 ` [PATCH 08/15] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 2:57 ` Anup Patel
2019-10-18 2:57 ` Anup Patel
2019-10-17 17:37 ` [PATCH 09/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:00 ` Anup Patel
2019-10-18 3:00 ` Anup Patel
2019-11-14 7:39 ` Paul Walmsley
2019-11-14 7:39 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 10/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-10-18 3:01 ` Anup Patel
2019-11-14 7:40 ` Paul Walmsley
2019-11-14 7:40 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 11/15] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-10-18 3:01 ` Anup Patel
2019-10-17 17:37 ` [PATCH 12/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:05 ` Anup Patel
2019-10-18 3:05 ` Anup Patel
2019-10-17 17:37 ` [PATCH 13/15] riscv: add nommu support Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:04 ` Anup Patel
2019-10-18 3:04 ` Anup Patel
2019-10-17 17:37 ` [PATCH 14/15] riscv: provide a flat image loader Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:06 ` Anup Patel
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-17 17:37 ` Christoph Hellwig
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:08 ` RISC-V nommu support v5 Anup Patel
2019-10-18 3:08 ` Anup Patel
2019-10-18 3:29 ` Paul Walmsley
2019-10-18 3:29 ` Paul Walmsley
2019-10-18 15:25 ` Christoph Hellwig [this message]
2019-10-18 15:25 ` Christoph Hellwig
2019-10-18 23:46 ` Paul Walmsley
2019-10-18 23:46 ` Paul Walmsley
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