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From: Andi Shyti <andi.shyti@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v2 1/2] drm/i915: Extract GT render power state management
Date: Wed, 23 Oct 2019 15:32:16 +0300	[thread overview]
Message-ID: <20191023123216.GA4125@intel.intel> (raw)
In-Reply-To: <157183266196.15766.14782680783428472038@skylake-alporthouse-com>

> >          * maximum clocks following a vblank miss (see do_rps_boost()).
> >          */
> >         if (!intel_state->rps_interactive) {
> > -               intel_rps_mark_interactive(dev_priv, true);
> > +               intel_rps_mark_interactive(&dev_priv->gt.rps, true);
> 
> I wonder if we can do &plane->vma->vm->gt->rps

agree, looks ugly, I could fix it by extracting rps. Shall I do
it now in a v3 or after the patch gets merged? As you can gues
I'd prefer doing after the patch is merged :)

Andi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Extract GT render power state management
Date: Wed, 23 Oct 2019 15:32:16 +0300	[thread overview]
Message-ID: <20191023123216.GA4125@intel.intel> (raw)
Message-ID: <20191023123216.yqWnWrBaw0YcX9kZYCdcj5jjqWJoa_16_LbunvyNpAg@z> (raw)
In-Reply-To: <157183266196.15766.14782680783428472038@skylake-alporthouse-com>

> >          * maximum clocks following a vblank miss (see do_rps_boost()).
> >          */
> >         if (!intel_state->rps_interactive) {
> > -               intel_rps_mark_interactive(dev_priv, true);
> > +               intel_rps_mark_interactive(&dev_priv->gt.rps, true);
> 
> I wonder if we can do &plane->vma->vm->gt->rps

agree, looks ugly, I could fix it by extracting rps. Shall I do
it now in a v3 or after the patch gets merged? As you can gues
I'd prefer doing after the patch is merged :)

Andi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-10-23 12:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-23  9:38 [PATCH 0/2] Extract rps and guc Andi Shyti
2019-10-23  9:38 ` [Intel-gfx] " Andi Shyti
2019-10-23  9:38 ` [PATCH 1/2] drm/i915: Extract GT render power state management Andi Shyti
2019-10-23  9:38   ` [Intel-gfx] " Andi Shyti
2019-10-23  9:38 ` [PATCH 2/2] drm/i915: Extract the GuC interrupt handlers Andi Shyti
2019-10-23  9:38   ` [Intel-gfx] " Andi Shyti
2019-10-23  9:50 ` [PATCH v2 1/2] drm/i915: Extract GT render power state management Andi Shyti
2019-10-23  9:50   ` [Intel-gfx] " Andi Shyti
2019-10-23  9:52   ` Andi Shyti
2019-10-23  9:52     ` [Intel-gfx] " Andi Shyti
2019-10-23 12:11   ` Chris Wilson
2019-10-23 12:11     ` [Intel-gfx] " Chris Wilson
2019-10-23 12:32     ` Andi Shyti [this message]
2019-10-23 12:32       ` Andi Shyti
2019-10-23 12:36       ` Chris Wilson
2019-10-23 12:36         ` [Intel-gfx] " Chris Wilson
2019-10-23 12:49         ` Andi Shyti
2019-10-23 12:49           ` [Intel-gfx] " Andi Shyti
2019-10-23 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for Extract rps and guc Patchwork
2019-10-23 17:48   ` [Intel-gfx] " Patchwork
2019-10-23 18:17 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-23 18:17   ` [Intel-gfx] " Patchwork
2019-10-24 10:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-24 10:24   ` [Intel-gfx] " Patchwork

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