From: Dan Carpenter <dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
To: Eric.Yang2-5C7GfCeVMHo@public.gmane.org
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [bug report] drm/amd/display: move wm ranges reporting to end of init hw
Date: Tue, 29 Oct 2019 21:30:22 +0300 [thread overview]
Message-ID: <20191029183022.GE17569@mwanda> (raw)
Hello Eric Yang,
This is a semi-automatic email about new static checker warnings.
The patch 622a88c8259e: "drm/amd/display: move wm ranges reporting to
end of init hw" from Sep 24, 2019, leads to the following Smatch
complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1308 dcn10_init_hw()
error: we previously assumed 'dc->clk_mgr' could be null (see line 1188)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
1187
1188 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
^^^^^^^^^^^
The existing code assumed this could be NULL. (Probably we should
remove this check?).
1189 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1190
1191 // Initialize the dccg
1192 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1193 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1194
1195 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1196
1197 REG_WRITE(REFCLK_CNTL, 0);
1198 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1199 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1200
1201 if (!dc->debug.disable_clock_gate) {
1202 /* enable all DCN clock gating */
1203 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1204
1205 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1206
1207 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1208 }
1209
1210 //Enable ability to power gate / don't force power on permanently
1211 dc->hwss.enable_power_gating_plane(hws, true);
1212
1213 return;
1214 }
1215
1216 if (!dcb->funcs->is_accelerated_mode(dcb))
1217 dc->hwss.disable_vga(dc->hwseq);
1218
1219 dc->hwss.bios_golden_init(dc);
1220 if (dc->ctx->dc_bios->fw_info_valid) {
1221 res_pool->ref_clocks.xtalin_clock_inKhz =
1222 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1223
1224 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1225 if (res_pool->dccg && res_pool->hubbub) {
1226
1227 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1228 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1229 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1230
1231 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1232 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1233 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1234 } else {
1235 // Not all ASICs have DCCG sw component
1236 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1237 res_pool->ref_clocks.xtalin_clock_inKhz;
1238 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1239 res_pool->ref_clocks.xtalin_clock_inKhz;
1240 }
1241 }
1242 } else
1243 ASSERT_CRITICAL(false);
1244
1245 for (i = 0; i < dc->link_count; i++) {
1246 /* Power up AND update implementation according to the
1247 * required signal (which may be different from the
1248 * default signal on connector).
1249 */
1250 struct dc_link *link = dc->links[i];
1251
1252 link->link_enc->funcs->hw_init(link->link_enc);
1253
1254 /* Check for enabled DIG to identify enabled display */
1255 if (link->link_enc->funcs->is_dig_enabled &&
1256 link->link_enc->funcs->is_dig_enabled(link->link_enc))
1257 link->link_status.link_active = true;
1258 }
1259
1260 /* Power gate DSCs */
1261 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1262 for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1263 if (dc->hwss.dsc_pg_control != NULL)
1264 dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1265 #endif
1266
1267 /* If taking control over from VBIOS, we may want to optimize our first
1268 * mode set, so we need to skip powering down pipes until we know which
1269 * pipes we want to use.
1270 * Otherwise, if taking control is not possible, we need to power
1271 * everything down.
1272 */
1273 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1274 dc->hwss.init_pipes(dc, dc->current_state);
1275 }
1276
1277 for (i = 0; i < res_pool->audio_count; i++) {
1278 struct audio *audio = res_pool->audios[i];
1279
1280 audio->funcs->hw_init(audio);
1281 }
1282
1283 if (abm != NULL) {
1284 abm->funcs->init_backlight(abm);
1285 abm->funcs->abm_init(abm);
1286 }
1287
1288 if (dmcu != NULL)
1289 dmcu->funcs->dmcu_init(dmcu);
1290
1291 if (abm != NULL && dmcu != NULL)
1292 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1293
1294 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1295 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1296
1297 if (!dc->debug.disable_clock_gate) {
1298 /* enable all DCN clock gating */
1299 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1300
1301 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1302
1303 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1304 }
1305
1306 dc->hwss.enable_power_gating_plane(dc->hwseq, true);
1307
1308 if (dc->clk_mgr->funcs->notify_wm_ranges)
^^^^^^^^^^^^^
The patch adds a new unconditional dereference.
1309 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1310
regards,
dan carpenter
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: Eric.Yang2@amd.com
Cc: amd-gfx@lists.freedesktop.org
Subject: [bug report] drm/amd/display: move wm ranges reporting to end of init hw
Date: Tue, 29 Oct 2019 21:30:22 +0300 [thread overview]
Message-ID: <20191029183022.GE17569@mwanda> (raw)
Message-ID: <20191029183022.Sx7NSjpdwtTalYgqgIqjLuTn2fY8jIDiV4XuSbr4ie8@z> (raw)
Hello Eric Yang,
This is a semi-automatic email about new static checker warnings.
The patch 622a88c8259e: "drm/amd/display: move wm ranges reporting to
end of init hw" from Sep 24, 2019, leads to the following Smatch
complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1308 dcn10_init_hw()
error: we previously assumed 'dc->clk_mgr' could be null (see line 1188)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
1187
1188 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
^^^^^^^^^^^
The existing code assumed this could be NULL. (Probably we should
remove this check?).
1189 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1190
1191 // Initialize the dccg
1192 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1193 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1194
1195 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1196
1197 REG_WRITE(REFCLK_CNTL, 0);
1198 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1199 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1200
1201 if (!dc->debug.disable_clock_gate) {
1202 /* enable all DCN clock gating */
1203 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1204
1205 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1206
1207 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1208 }
1209
1210 //Enable ability to power gate / don't force power on permanently
1211 dc->hwss.enable_power_gating_plane(hws, true);
1212
1213 return;
1214 }
1215
1216 if (!dcb->funcs->is_accelerated_mode(dcb))
1217 dc->hwss.disable_vga(dc->hwseq);
1218
1219 dc->hwss.bios_golden_init(dc);
1220 if (dc->ctx->dc_bios->fw_info_valid) {
1221 res_pool->ref_clocks.xtalin_clock_inKhz =
1222 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1223
1224 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1225 if (res_pool->dccg && res_pool->hubbub) {
1226
1227 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
1228 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1229 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
1230
1231 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
1232 res_pool->ref_clocks.dccg_ref_clock_inKhz,
1233 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
1234 } else {
1235 // Not all ASICs have DCCG sw component
1236 res_pool->ref_clocks.dccg_ref_clock_inKhz =
1237 res_pool->ref_clocks.xtalin_clock_inKhz;
1238 res_pool->ref_clocks.dchub_ref_clock_inKhz =
1239 res_pool->ref_clocks.xtalin_clock_inKhz;
1240 }
1241 }
1242 } else
1243 ASSERT_CRITICAL(false);
1244
1245 for (i = 0; i < dc->link_count; i++) {
1246 /* Power up AND update implementation according to the
1247 * required signal (which may be different from the
1248 * default signal on connector).
1249 */
1250 struct dc_link *link = dc->links[i];
1251
1252 link->link_enc->funcs->hw_init(link->link_enc);
1253
1254 /* Check for enabled DIG to identify enabled display */
1255 if (link->link_enc->funcs->is_dig_enabled &&
1256 link->link_enc->funcs->is_dig_enabled(link->link_enc))
1257 link->link_status.link_active = true;
1258 }
1259
1260 /* Power gate DSCs */
1261 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1262 for (i = 0; i < res_pool->res_cap->num_dsc; i++)
1263 if (dc->hwss.dsc_pg_control != NULL)
1264 dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
1265 #endif
1266
1267 /* If taking control over from VBIOS, we may want to optimize our first
1268 * mode set, so we need to skip powering down pipes until we know which
1269 * pipes we want to use.
1270 * Otherwise, if taking control is not possible, we need to power
1271 * everything down.
1272 */
1273 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
1274 dc->hwss.init_pipes(dc, dc->current_state);
1275 }
1276
1277 for (i = 0; i < res_pool->audio_count; i++) {
1278 struct audio *audio = res_pool->audios[i];
1279
1280 audio->funcs->hw_init(audio);
1281 }
1282
1283 if (abm != NULL) {
1284 abm->funcs->init_backlight(abm);
1285 abm->funcs->abm_init(abm);
1286 }
1287
1288 if (dmcu != NULL)
1289 dmcu->funcs->dmcu_init(dmcu);
1290
1291 if (abm != NULL && dmcu != NULL)
1292 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1293
1294 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1295 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1296
1297 if (!dc->debug.disable_clock_gate) {
1298 /* enable all DCN clock gating */
1299 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1300
1301 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1302
1303 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1304 }
1305
1306 dc->hwss.enable_power_gating_plane(dc->hwseq, true);
1307
1308 if (dc->clk_mgr->funcs->notify_wm_ranges)
^^^^^^^^^^^^^
The patch adds a new unconditional dereference.
1309 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1310
regards,
dan carpenter
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next reply other threads:[~2019-10-29 18:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-29 18:30 Dan Carpenter [this message]
2019-10-29 18:30 ` [bug report] drm/amd/display: move wm ranges reporting to end of init hw Dan Carpenter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191029183022.GE17569@mwanda \
--to=dan.carpenter-qhclzuegtsvqt0dzr+alfa@public.gmane.org \
--cc=Eric.Yang2-5C7GfCeVMHo@public.gmane.org \
--cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.