From: Peter Zijlstra <peterz@infradead.org>
To: "Kang, Luwei" <luwei.kang@intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"rkrcmar@redhat.com" <rkrcmar@redhat.com>,
"Christopherson, Sean J" <sean.j.christopherson@intel.com>,
"vkuznets@redhat.com" <vkuznets@redhat.com>,
"wanpengli@tencent.com" <wanpengli@tencent.com>,
"jmattson@google.com" <jmattson@google.com>,
"joro@8bytes.org" <joro@8bytes.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"bp@alien8.de" <bp@alien8.de>, "hpa@zytor.com" <hpa@zytor.com>,
"x86@kernel.org" <x86@kernel.org>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"acme@kernel.org" <acme@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>,
"jolsa@redhat.com" <jolsa@redhat.com>,
"namhyung@kernel.org" <namhyung@kernel.org>
Subject: Re: [PATCH v1 3/8] KVM: x86: Allocate performance counter for PEBS event
Date: Wed, 30 Oct 2019 10:49:41 +0100 [thread overview]
Message-ID: <20191030094941.GQ4097@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <82D7661F83C1A047AF7DC287873BF1E173835B1A@SHSMSX104.ccr.corp.intel.com>
On Wed, Oct 30, 2019 at 04:06:36AM +0000, Kang, Luwei wrote:
> > > static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
> > > unsigned config, bool exclude_user,
> > > bool exclude_kernel, bool intr,
> > > - bool in_tx, bool in_tx_cp)
> > > + bool in_tx, bool in_tx_cp, bool pebs)
> > > {
> > > struct perf_event *event;
> > > struct perf_event_attr attr = {
> > > @@ -111,9 +111,12 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
> > > .exclude_user = exclude_user,
> > > .exclude_kernel = exclude_kernel,
> > > .config = config,
> > > + .precise_ip = pebs ? 1 : 0,
> > > + .aux_output = pebs ? 1 : 0,
> >
> > srsly?
>
> Hi Peter,
> Thanks for review. For aux_output, I think it should be set 1 when the guest wants to enabled PEBS by Intel PT.
> For precise_ip, it is the precise level in perf and set by perf command line in KVM guest, this may not reflect the accurate value (can be 0~3) here. Here set to 1 is used to allocate a counter for PEBS event and set the MSR_IA32_PEBS_ENABLE register. For PMU virtualization, KVM will trap the guest's write operation to PMU registers and allocate/free event counter from host if a counter enable/disable in guest. We can't always deduce the exact parameter of perf command line from the value of the guest writers to the register.
Please, teach your MUA to wrap on 78 chars.
The thing I really fell over is the gratuitous 'bool ? 1 : 0'. But yes,
the aux_output without a group leader is dead wrong. We'll go fix
perf_event_create_kernel_counter() to refuse that.
next prev parent reply other threads:[~2019-10-30 9:50 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-27 23:11 [PATCH v1 0/8] PEBS enabling in KVM guest Luwei Kang
2019-10-27 23:11 ` [PATCH v1 1/8] KVM: x86: Add base address parameter for get_fixed_pmc function Luwei Kang
2019-10-27 23:11 ` [PATCH v1 2/8] KVM: x86: PEBS output to Intel PT MSRs emulation Luwei Kang
2019-10-29 15:02 ` Peter Zijlstra
2019-10-30 4:06 ` Kang, Luwei
2019-10-27 23:11 ` [PATCH v1 3/8] KVM: x86: Allocate performance counter for PEBS event Luwei Kang
2019-10-29 14:46 ` Peter Zijlstra
2019-10-30 4:06 ` Kang, Luwei
2019-10-30 6:42 ` Alexander Shishkin
2019-10-30 6:49 ` Kang, Luwei
2019-10-30 9:51 ` Peter Zijlstra
2019-10-30 9:50 ` Peter Zijlstra
2019-10-30 9:49 ` Peter Zijlstra [this message]
2019-10-30 13:41 ` Alexander Shishkin
2019-10-31 11:10 ` Kang, Luwei
2019-11-06 7:44 ` Kang, Luwei
2019-10-27 23:11 ` [PATCH v1 4/8] KVM: x86: Aviod clear the PEBS counter when PEBS enabled in guest Luwei Kang
2019-10-29 14:55 ` Peter Zijlstra
2019-10-30 4:06 ` Kang, Luwei
2019-10-27 23:11 ` [PATCH v1 5/8] KVM: X86: Expose PDCM cpuid to guest Luwei Kang
2019-10-27 23:11 ` [PATCH v1 6/8] KVM: X86: MSR_IA32_PERF_CAPABILITIES MSR emulation Luwei Kang
2019-10-27 23:11 ` [PATCH v1 7/8] KVM: x86: Expose PEBS feature to guest Luwei Kang
2019-10-29 15:05 ` Peter Zijlstra
2019-10-30 4:07 ` Kang, Luwei
2019-10-30 9:52 ` Peter Zijlstra
2019-10-31 4:21 ` Kang, Luwei
2019-10-27 23:11 ` [PATCH v1 8/8] perf/x86: Add event owner check when PEBS output to Intel PT Luwei Kang
2019-10-29 15:13 ` Peter Zijlstra
2019-10-30 4:07 ` Kang, Luwei
2019-10-30 9:54 ` Peter Zijlstra
2019-10-31 6:55 ` Kang, Luwei
2019-10-31 7:39 ` Alexander Shishkin
2019-10-31 10:31 ` Kang, Luwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191030094941.GQ4097@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=bp@alien8.de \
--cc=hpa@zytor.com \
--cc=jmattson@google.com \
--cc=jolsa@redhat.com \
--cc=joro@8bytes.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luwei.kang@intel.com \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=pbonzini@redhat.com \
--cc=rkrcmar@redhat.com \
--cc=sean.j.christopherson@intel.com \
--cc=tglx@linutronix.de \
--cc=thomas.lendacky@amd.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.