From: Shawn Guo <shawnguo@kernel.org>
To: Peng Fan <peng.fan@nxp.com>
Cc: "mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
Abel Vesa <abel.vesa@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>,
Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leonard Crestez <leonard.crestez@nxp.com>
Subject: Re: [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels
Date: Mon, 4 Nov 2019 09:11:07 +0800 [thread overview]
Message-ID: <20191104011106.GD24620@dragon> (raw)
In-Reply-To: <1572231902-30230-1-git-send-email-peng.fan@nxp.com>
On Mon, Oct 28, 2019 at 03:08:34AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
>
> According to the current imx_clk_sccg_pll design, it uses both
> bypass1/2, however set bypass2 as 1 is not correct, because it will
> make sys[x]_pll_out use wrong parent and might access wrong registers.
>
> So correct bypass2 to 0 and fix sys3_pll_out_sels.
>
> Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Peng Fan <peng.fan@nxp.com>
Cc: Abel Vesa <abel.vesa@nxp.com>, Anson Huang <anson.huang@nxp.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
Leonard Crestez <leonard.crestez@nxp.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels
Date: Mon, 4 Nov 2019 09:11:07 +0800 [thread overview]
Message-ID: <20191104011106.GD24620@dragon> (raw)
In-Reply-To: <1572231902-30230-1-git-send-email-peng.fan@nxp.com>
On Mon, Oct 28, 2019 at 03:08:34AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
>
> According to the current imx_clk_sccg_pll design, it uses both
> bypass1/2, however set bypass2 as 1 is not correct, because it will
> make sys[x]_pll_out use wrong parent and might access wrong registers.
>
> So correct bypass2 to 0 and fix sys3_pll_out_sels.
>
> Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
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next prev parent reply other threads:[~2019-11-04 1:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 3:08 [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels Peng Fan
2019-10-28 3:08 ` Peng Fan
2019-11-04 1:11 ` Shawn Guo [this message]
2019-11-04 1:11 ` Shawn Guo
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