From: Thierry Reding <thierry.reding@gmail.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 2/5] drm/dsi: add missing DSI data types
Date: Mon, 4 Nov 2019 16:24:11 +0100 [thread overview]
Message-ID: <20191104152411.GB1602887@ulmo> (raw)
In-Reply-To: <20191028150047.22048-2-jani.nikula@intel.com>
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On Mon, Oct 28, 2019 at 05:00:44PM +0200, Jani Nikula wrote:
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index f237d80828c3..3f33f02571fd 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
Actually, it looks like the ordering is by lowest-significant nibble
first, then by highest-significant nibble, so maybe there's some logic
to this after all.
Hmm... that's mostly true, except for 0x07 and 0x08... anyway, the new
enumeration values and names match the specification, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/5] drm/dsi: add missing DSI data types
Date: Mon, 4 Nov 2019 16:24:11 +0100 [thread overview]
Message-ID: <20191104152411.GB1602887@ulmo> (raw)
Message-ID: <20191104152411.vUqViG6nPdV4kLjReXOdkSq76n7OCWNslD8sMMeE6eU@z> (raw)
In-Reply-To: <20191028150047.22048-2-jani.nikula@intel.com>
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On Mon, Oct 28, 2019 at 05:00:44PM +0200, Jani Nikula wrote:
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index f237d80828c3..3f33f02571fd 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
Actually, it looks like the ordering is by lowest-significant nibble
first, then by highest-significant nibble, so maybe there's some logic
to this after all.
Hmm... that's mostly true, except for 0x07 and 0x08... anyway, the new
enumeration values and names match the specification, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-04 15:24 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 15:00 [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-10-28 15:00 ` Jani Nikula
2019-10-28 15:00 ` [PATCH v2 2/5] drm/dsi: add missing DSI data types Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-10-30 8:28 ` Kulkarni, Vandita
2019-10-30 8:28 ` [Intel-gfx] " Kulkarni, Vandita
2019-10-30 8:28 ` Kulkarni, Vandita
2019-11-04 15:24 ` Thierry Reding [this message]
2019-11-04 15:24 ` [Intel-gfx] " Thierry Reding
2019-10-28 15:00 ` [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-10-28 15:00 ` Jani Nikula
2019-11-04 15:29 ` Thierry Reding
2019-11-04 15:29 ` [Intel-gfx] " Thierry Reding
2019-11-04 15:29 ` Thierry Reding
2019-11-05 9:18 ` Thierry Reding
2019-11-05 9:18 ` Thierry Reding
2019-11-05 14:06 ` Jani Nikula
2019-11-05 14:06 ` [Intel-gfx] " Jani Nikula
2019-11-05 14:06 ` Jani Nikula
2019-10-28 15:00 ` [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-10-28 15:00 ` Jani Nikula
2019-11-05 9:42 ` [Intel-gfx] " Thierry Reding
2019-11-05 9:42 ` Thierry Reding
2019-10-28 15:00 ` [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-11-05 9:55 ` Thierry Reding
2019-11-05 9:55 ` [Intel-gfx] " Thierry Reding
2019-10-28 19:17 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions Patchwork
2019-10-28 19:17 ` [Intel-gfx] " Patchwork
2019-10-28 19:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-28 19:37 ` [Intel-gfx] " Patchwork
2019-10-29 14:04 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-29 14:04 ` [Intel-gfx] " Patchwork
2019-11-04 14:07 ` [PATCH v2 1/5] " Jani Nikula
2019-11-04 14:07 ` [Intel-gfx] " Jani Nikula
2019-11-07 13:21 ` Jani Nikula
2019-11-07 13:21 ` [Intel-gfx] " Jani Nikula
2019-11-04 15:20 ` Thierry Reding
2019-11-04 15:20 ` [Intel-gfx] " Thierry Reding
2019-11-04 15:20 ` Thierry Reding
2019-11-05 9:18 ` Jani Nikula
2019-11-05 9:18 ` Jani Nikula
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