From: Andi Shyti <andi.shyti@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 08/10] drm/i915/gt: Defer engine registration until fully initialised
Date: Tue, 5 Nov 2019 17:23:56 +0200 [thread overview]
Message-ID: <20191105152356.GA3331@intel.intel> (raw)
In-Reply-To: <20191105092115.11451-8-chris@chris-wilson.co.uk>
Hi Chris,
On Tue, Nov 05, 2019 at 09:21:13AM +0000, Chris Wilson wrote:
> Only add the engine to the available set of uabi engines once it has
> been fully initialised and we know we want it in the public set.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
Acked-by: Andi Shyti <andi.shyti@intel.com>
Andi
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WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/10] drm/i915/gt: Defer engine registration until fully initialised
Date: Tue, 5 Nov 2019 17:23:56 +0200 [thread overview]
Message-ID: <20191105152356.GA3331@intel.intel> (raw)
Message-ID: <20191105152356._Ewzy5MBCrdDB_zwLCdUU7gC9svJTC-mu-54pj_Z180@z> (raw)
In-Reply-To: <20191105092115.11451-8-chris@chris-wilson.co.uk>
Hi Chris,
On Tue, Nov 05, 2019 at 09:21:13AM +0000, Chris Wilson wrote:
> Only add the engine to the available set of uabi engines once it has
> been fully initialised and we know we want it in the public set.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
Acked-by: Andi Shyti <andi.shyti@intel.com>
Andi
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-05 15:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 9:21 [PATCH 01/10] drm/i915: Use a ctor for TYPESAFE_BY_RCU i915_request Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 02/10] drm/i915/selftests: Perform some basic cycle counting of MI ops Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 03/10] drm/i915/selftests: Mock the engine sorting for easy validation Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 04/10] drm/i915: Drop GEM context as a direct link from i915_request Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 05/10] drm/i915: Push the use-semaphore marker onto the intel_context Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 06/10] drm/i915: Remove i915->kernel_context Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 07/10] drm/i915: Move i915_gem_init_contexts() earlier Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 08/10] drm/i915/gt: Defer engine registration until fully initialised Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 15:23 ` Andi Shyti [this message]
2019-11-05 15:23 ` Andi Shyti
2019-11-05 9:21 ` [PATCH 09/10] drm/i915/gt: Pull GT initialisation under intel_gt_init() Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 9:21 ` [PATCH 10/10] drm/i915/gt: Merge engine init/setup loops Chris Wilson
2019-11-05 9:21 ` [Intel-gfx] " Chris Wilson
2019-11-05 10:00 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Use a ctor for TYPESAFE_BY_RCU i915_request Patchwork
2019-11-05 10:00 ` [Intel-gfx] " Patchwork
2019-11-05 10:22 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-11-05 10:22 ` [Intel-gfx] " Patchwork
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