* [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL
@ 2019-10-20 18:21 Hans de Goede
2019-10-20 19:10 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Hans de Goede @ 2019-10-20 18:21 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ville Syrjälä
Cc: Hans de Goede, intel-gfx, dri-devel
Fastboot is not working on an Asus T100HA, it gives the following
relevant messages / errors:
dsi pll div 000201e6, ctrl 80080100
fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100)
fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6)
The problem seems to be that the GOP picks 5 for the P divisor, where as
we end up picking 4.
This commit fixes this by first checking of the currently configured
DSI PLL settings match the desired pclk and if they do, stick with
the currently configured PLL settings.
Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside
config->dsi_pll, so they are set to the GOP / previous values after
calling it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index 95f39cd0ce02..4a09edecd597 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int ret;
- u32 dsi_clk;
-
- dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
- intel_dsi->lane_count);
+ u32 dsi_clk, current_pclk;
- ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
- if (ret) {
- DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
- return ret;
+ /*
+ * For exact matches, the GOP may pick another set of divisors
+ * then we do, if the GOP settings are an exact match keep them.
+ */
+ current_pclk = vlv_dsi_get_pclk(encoder, config);
+ if (current_pclk == intel_dsi->pclk) {
+ config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK;
+ } else {
+ dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
+ intel_dsi->pixel_format,
+ intel_dsi->lane_count);
+
+ ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
+ if (ret) {
+ DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
+ return ret;
+ }
}
if (intel_dsi->ports & (1 << PORT_A))
--
2.23.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL 2019-10-20 18:21 [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL Hans de Goede @ 2019-10-20 19:10 ` Patchwork 2019-10-20 21:23 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-07 11:24 ` Ville Syrjälä 2 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2019-10-20 19:10 UTC (permalink / raw) To: Hans de Goede; +Cc: intel-gfx == Series Details == Series: drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL URL : https://patchwork.freedesktop.org/series/68286/ State : success == Summary == CI Bug Log - changes from CI_DRM_7136 -> Patchwork_14898 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/index.html Known issues ------------ Here are the changes found in Patchwork_14898 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_active: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-cml-u2/igt@i915_selftest@live_active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-cml-u2/igt@i915_selftest@live_active.html * igt@i915_selftest@live_execlists: - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] / [fdo#112065]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-apl-guc/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-apl-guc/igt@i915_selftest@live_execlists.html - fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927] / [fdo#112065]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-bxt-dsi/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-bxt-dsi/igt@i915_selftest@live_execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html #### Possible fixes #### * igt@gem_ctx_create@basic: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-icl-u3/igt@gem_ctx_create@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-icl-u3/igt@gem_ctx_create@basic.html * igt@gem_ctx_switch@legacy-render: - fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#111381]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html * igt@i915_selftest@live_coherency: - fi-kbl-soraka: [TIMEOUT][13] ([fdo#111944]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-kbl-soraka/igt@i915_selftest@live_coherency.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-kbl-soraka/igt@i915_selftest@live_coherency.html * igt@i915_selftest@live_hangcheck: - {fi-icl-u4}: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-icl-u4/igt@i915_selftest@live_hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-icl-u4/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747 [fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944 [fdo#112065]: https://bugs.freedesktop.org/show_bug.cgi?id=112065 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7136 -> Patchwork_14898 CI-20190529: 20190529 CI_DRM_7136: 6f7e6926bb09b1ec80c5a3d44a930d690dd09d9c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5234: 1205552397bd8a19dc6e5abdaa727cc091dabbfe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14898: 68b5ebbe90d4782059c5ee8f802a374240743d94 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 68b5ebbe90d4 drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL 2019-10-20 18:21 [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL Hans de Goede 2019-10-20 19:10 ` ✓ Fi.CI.BAT: success for " Patchwork @ 2019-10-20 21:23 ` Patchwork 2019-11-07 11:24 ` Ville Syrjälä 2 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2019-10-20 21:23 UTC (permalink / raw) To: Hans de Goede; +Cc: intel-gfx == Series Details == Series: drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL URL : https://patchwork.freedesktop.org/series/68286/ State : success == Summary == CI Bug Log - changes from CI_DRM_7136_full -> Patchwork_14898_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_14898_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@reset-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-snb2/igt@gem_eio@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-snb2/igt@gem_eio@reset-stress.html * igt@gem_exec_reuse@baggage: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([fdo#103540]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-hsw1/igt@gem_exec_reuse@baggage.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-hsw4/igt@gem_exec_reuse@baggage.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd2.html * igt@gem_mmap_gtt@hang: - shard-snb: [PASS][9] -> [INCOMPLETE][10] ([fdo#105411]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-snb6/igt@gem_mmap_gtt@hang.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-snb6/igt@gem_mmap_gtt@hang.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-kbl: [PASS][11] -> [FAIL][12] ([fdo#112037]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-kbl6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-kbl4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_userptr_blits@sync-unmap: - shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-hsw4/igt@gem_userptr_blits@sync-unmap.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb1/igt@i915_selftest@live_hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb3/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-kbl4/igt@i915_suspend@forcewake.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-kbl3/igt@i915_suspend@forcewake.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103232]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167] / [fdo#110378]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-tilingchange.html * igt@kms_plane@plane-panning-top-left-pipe-a-planes: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#103166]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl5/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl8/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [fdo#110403]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb8/igt@kms_psr@psr2_sprite_blt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +5 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-iclb: [INCOMPLETE][33] ([fdo#107713]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [SKIP][35] ([fdo#111325]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb8/igt@gem_exec_schedule@wide-bsd.html * igt@gem_exec_whisper@normal: - {shard-tglb}: [INCOMPLETE][37] -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-tglb8/igt@gem_exec_whisper@normal.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-tglb8/igt@gem_exec_whisper@normal.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing: - {shard-tglb}: [TIMEOUT][39] ([fdo#112068 ]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-tglb4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-tglb2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][41] ([fdo#108566]) -> [PASS][42] +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-apl4/igt@gem_workarounds@suspend-resume-context.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-apl4/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [INCOMPLETE][43] ([fdo#104108]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html * {igt@i915_pm_dc@dc6-psr}: - shard-iclb: [FAIL][45] ([fdo#110548]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb8/igt@i915_pm_dc@dc6-psr.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb1/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [INCOMPLETE][47] ([fdo#104108] / [fdo#107807]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl10/igt@i915_pm_rpm@system-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl1/igt@i915_pm_rpm@system-suspend.html * igt@i915_selftest@live_execlists: - shard-apl: [INCOMPLETE][49] ([fdo#103927] / [fdo#112065]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-apl7/igt@i915_selftest@live_execlists.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-apl6/igt@i915_selftest@live_execlists.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-apl: [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-apl3/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-apl1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [FAIL][53] ([fdo#105363]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [FAIL][55] ([fdo#103167]) -> [PASS][56] +7 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - {shard-tglb}: [FAIL][57] ([fdo#103167]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][59] ([fdo#108145] / [fdo#110403]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [FAIL][61] ([fdo#103166]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-apl: [FAIL][65] ([fdo#99912]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-apl1/igt@kms_setmode@basic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-apl8/igt@kms_setmode@basic.html * igt@kms_universal_plane@universal-plane-pipe-c-functional: - shard-skl: [FAIL][67] ([fdo#111134]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-skl1/igt@kms_universal_plane@universal-plane-pipe-c-functional.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-skl7/igt@kms_universal_plane@universal-plane-pipe-c-functional.html * igt@kms_vblank@pipe-d-ts-continuation-suspend: - {shard-tglb}: [INCOMPLETE][69] ([fdo#111850]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-tglb6/igt@kms_vblank@pipe-d-ts-continuation-suspend.html * igt@perf@oa-exponents: - shard-glk: [FAIL][71] ([fdo#105483]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-glk5/igt@perf@oa-exponents.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-glk4/igt@perf@oa-exponents.html * igt@prime_busy@after-bsd2: - shard-iclb: [SKIP][73] ([fdo#109276]) -> [PASS][74] +14 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb6/igt@prime_busy@after-bsd2.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb4/igt@prime_busy@after-bsd2.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [SKIP][75] ([fdo#109276]) -> [FAIL][76] ([fdo#111329]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html * igt@gem_mocs_settings@mocs-reset-bsd2: - shard-iclb: [SKIP][77] ([fdo#109276]) -> [FAIL][78] ([fdo#111330]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb3/igt@gem_mocs_settings@mocs-reset-bsd2.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [DMESG-WARN][79] ([fdo#107724]) -> [SKIP][80] ([fdo#109349]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7136/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661 [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548 [fdo#111134]: https://bugs.freedesktop.org/show_bug.cgi?id=111134 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329 [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330 [fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597 [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646 [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747 [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781 [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832 [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850 [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037 [fdo#112065]: https://bugs.freedesktop.org/show_bug.cgi?id=112065 [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7136 -> Patchwork_14898 CI-20190529: 20190529 CI_DRM_7136: 6f7e6926bb09b1ec80c5a3d44a930d690dd09d9c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5234: 1205552397bd8a19dc6e5abdaa727cc091dabbfe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14898: 68b5ebbe90d4782059c5ee8f802a374240743d94 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14898/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:24 ` Ville Syrjälä 0 siblings, 0 replies; 9+ messages in thread From: Ville Syrjälä @ 2019-11-07 11:24 UTC (permalink / raw) To: Hans de Goede; +Cc: intel-gfx, dri-devel On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > Fastboot is not working on an Asus T100HA, it gives the following > relevant messages / errors: > > dsi pll div 000201e6, ctrl 80080100 > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > The problem seems to be that the GOP picks 5 for the P divisor, where as > we end up picking 4. > > This commit fixes this by first checking of the currently configured > DSI PLL settings match the desired pclk and if they do, stick with > the currently configured PLL settings. > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > config->dsi_pll, so they are set to the GOP / previous values after > calling it. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > index 95f39cd0ce02..4a09edecd597 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > int ret; > - u32 dsi_clk; > - > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > - intel_dsi->lane_count); > + u32 dsi_clk, current_pclk; > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > - if (ret) { > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > - return ret; > + /* > + * For exact matches, the GOP may pick another set of divisors > + * then we do, if the GOP settings are an exact match keep them. > + */ > + current_pclk = vlv_dsi_get_pclk(encoder, config); One is not allowed to touch the hw in .compute_config(). The question is why does the GOP generate a different P divider? Does it use a slightly different clock? > + if (current_pclk == intel_dsi->pclk) { > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > + } else { > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > + intel_dsi->pixel_format, > + intel_dsi->lane_count); > + > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > + if (ret) { > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > + return ret; > + } > } > > if (intel_dsi->ports & (1 << PORT_A)) > -- > 2.23.0 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:24 ` Ville Syrjälä 0 siblings, 0 replies; 9+ messages in thread From: Ville Syrjälä @ 2019-11-07 11:24 UTC (permalink / raw) To: Hans de Goede; +Cc: intel-gfx, dri-devel On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > Fastboot is not working on an Asus T100HA, it gives the following > relevant messages / errors: > > dsi pll div 000201e6, ctrl 80080100 > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > The problem seems to be that the GOP picks 5 for the P divisor, where as > we end up picking 4. > > This commit fixes this by first checking of the currently configured > DSI PLL settings match the desired pclk and if they do, stick with > the currently configured PLL settings. > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > config->dsi_pll, so they are set to the GOP / previous values after > calling it. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > index 95f39cd0ce02..4a09edecd597 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > int ret; > - u32 dsi_clk; > - > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > - intel_dsi->lane_count); > + u32 dsi_clk, current_pclk; > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > - if (ret) { > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > - return ret; > + /* > + * For exact matches, the GOP may pick another set of divisors > + * then we do, if the GOP settings are an exact match keep them. > + */ > + current_pclk = vlv_dsi_get_pclk(encoder, config); One is not allowed to touch the hw in .compute_config(). The question is why does the GOP generate a different P divider? Does it use a slightly different clock? > + if (current_pclk == intel_dsi->pclk) { > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > + } else { > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > + intel_dsi->pixel_format, > + intel_dsi->lane_count); > + > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > + if (ret) { > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > + return ret; > + } > } > > if (intel_dsi->ports & (1 << PORT_A)) > -- > 2.23.0 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:24 ` Ville Syrjälä 0 siblings, 0 replies; 9+ messages in thread From: Ville Syrjälä @ 2019-11-07 11:24 UTC (permalink / raw) To: Hans de Goede; +Cc: intel-gfx, dri-devel, Rodrigo Vivi On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > Fastboot is not working on an Asus T100HA, it gives the following > relevant messages / errors: > > dsi pll div 000201e6, ctrl 80080100 > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > The problem seems to be that the GOP picks 5 for the P divisor, where as > we end up picking 4. > > This commit fixes this by first checking of the currently configured > DSI PLL settings match the desired pclk and if they do, stick with > the currently configured PLL settings. > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > config->dsi_pll, so they are set to the GOP / previous values after > calling it. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > index 95f39cd0ce02..4a09edecd597 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > int ret; > - u32 dsi_clk; > - > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > - intel_dsi->lane_count); > + u32 dsi_clk, current_pclk; > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > - if (ret) { > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > - return ret; > + /* > + * For exact matches, the GOP may pick another set of divisors > + * then we do, if the GOP settings are an exact match keep them. > + */ > + current_pclk = vlv_dsi_get_pclk(encoder, config); One is not allowed to touch the hw in .compute_config(). The question is why does the GOP generate a different P divider? Does it use a slightly different clock? > + if (current_pclk == intel_dsi->pclk) { > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > + } else { > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > + intel_dsi->pixel_format, > + intel_dsi->lane_count); > + > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > + if (ret) { > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > + return ret; > + } > } > > if (intel_dsi->ports & (1 << PORT_A)) > -- > 2.23.0 -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:37 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2019-11-07 11:37 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, dri-devel On Thu, Nov 7, 2019 at 12:24 PM Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > > Fastboot is not working on an Asus T100HA, it gives the following > > relevant messages / errors: > > > > dsi pll div 000201e6, ctrl 80080100 > > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > > > The problem seems to be that the GOP picks 5 for the P divisor, where as > > we end up picking 4. > > > > This commit fixes this by first checking of the currently configured > > DSI PLL settings match the desired pclk and if they do, stick with > > the currently configured PLL settings. > > > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > > config->dsi_pll, so they are set to the GOP / previous values after > > calling it. > > > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > --- > > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > > 1 file changed, 18 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > index 95f39cd0ce02..4a09edecd597 100644 > > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > int ret; > > - u32 dsi_clk; > > - > > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > > - intel_dsi->lane_count); > > + u32 dsi_clk, current_pclk; > > > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > - if (ret) { > > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > - return ret; > > + /* > > + * For exact matches, the GOP may pick another set of divisors > > + * then we do, if the GOP settings are an exact match keep them. > > + */ > > + current_pclk = vlv_dsi_get_pclk(encoder, config); > > One is not allowed to touch the hw in .compute_config(). > > The question is why does the GOP generate a different P divider? > Does it use a slightly different clock? Clock mismatches that we can ignore should be fixed in the fast-set compare/fixup function, not here in compute_config. There's already plenty of fixup code for other clocks (e.g. dp) in there. And yes no touching hw, ever, from anything run in atomic_check context. -Daniel > > > > + if (current_pclk == intel_dsi->pclk) { > > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > > + } else { > > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > > + intel_dsi->pixel_format, > > + intel_dsi->lane_count); > > + > > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > + if (ret) { > > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > + return ret; > > + } > > } > > > > if (intel_dsi->ports & (1 << PORT_A)) > > -- > > 2.23.0 > > -- > Ville Syrjälä > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:37 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2019-11-07 11:37 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, dri-devel On Thu, Nov 7, 2019 at 12:24 PM Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > > Fastboot is not working on an Asus T100HA, it gives the following > > relevant messages / errors: > > > > dsi pll div 000201e6, ctrl 80080100 > > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > > > The problem seems to be that the GOP picks 5 for the P divisor, where as > > we end up picking 4. > > > > This commit fixes this by first checking of the currently configured > > DSI PLL settings match the desired pclk and if they do, stick with > > the currently configured PLL settings. > > > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > > config->dsi_pll, so they are set to the GOP / previous values after > > calling it. > > > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > --- > > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > > 1 file changed, 18 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > index 95f39cd0ce02..4a09edecd597 100644 > > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > int ret; > > - u32 dsi_clk; > > - > > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > > - intel_dsi->lane_count); > > + u32 dsi_clk, current_pclk; > > > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > - if (ret) { > > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > - return ret; > > + /* > > + * For exact matches, the GOP may pick another set of divisors > > + * then we do, if the GOP settings are an exact match keep them. > > + */ > > + current_pclk = vlv_dsi_get_pclk(encoder, config); > > One is not allowed to touch the hw in .compute_config(). > > The question is why does the GOP generate a different P divider? > Does it use a slightly different clock? Clock mismatches that we can ignore should be fixed in the fast-set compare/fixup function, not here in compute_config. There's already plenty of fixup code for other clocks (e.g. dp) in there. And yes no touching hw, ever, from anything run in atomic_check context. -Daniel > > > > + if (current_pclk == intel_dsi->pclk) { > > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > > + } else { > > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > > + intel_dsi->pixel_format, > > + intel_dsi->lane_count); > > + > > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > + if (ret) { > > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > + return ret; > > + } > > } > > > > if (intel_dsi->ports & (1 << PORT_A)) > > -- > > 2.23.0 > > -- > Ville Syrjälä > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL @ 2019-11-07 11:37 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2019-11-07 11:37 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Hans de Goede, intel-gfx, dri-devel On Thu, Nov 7, 2019 at 12:24 PM Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Sun, Oct 20, 2019 at 08:21:32PM +0200, Hans de Goede wrote: > > Fastboot is not working on an Asus T100HA, it gives the following > > relevant messages / errors: > > > > dsi pll div 000201e6, ctrl 80080100 > > fastset mismatch in dsi_pll.ctrl (expected 0x80100100, found 0x80080100) > > fastset mismatch in dsi_pll.div (expected 0x0002008e, found 0x000201e6) > > > > The problem seems to be that the GOP picks 5 for the P divisor, where as > > we end up picking 4. > > > > This commit fixes this by first checking of the currently configured > > DSI PLL settings match the desired pclk and if they do, stick with > > the currently configured PLL settings. > > > > Note that vlv_dsi_get_pclk() stores the read ctrl and div values inside > > config->dsi_pll, so they are set to the GOP / previous values after > > calling it. > > > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > --- > > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 26 +++++++++++++++------- > > 1 file changed, 18 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > index 95f39cd0ce02..4a09edecd597 100644 > > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > @@ -119,15 +119,25 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > int ret; > > - u32 dsi_clk; > > - > > - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, > > - intel_dsi->lane_count); > > + u32 dsi_clk, current_pclk; > > > > - ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > - if (ret) { > > - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > - return ret; > > + /* > > + * For exact matches, the GOP may pick another set of divisors > > + * then we do, if the GOP settings are an exact match keep them. > > + */ > > + current_pclk = vlv_dsi_get_pclk(encoder, config); > > One is not allowed to touch the hw in .compute_config(). > > The question is why does the GOP generate a different P divider? > Does it use a slightly different clock? Clock mismatches that we can ignore should be fixed in the fast-set compare/fixup function, not here in compute_config. There's already plenty of fixup code for other clocks (e.g. dp) in there. And yes no touching hw, ever, from anything run in atomic_check context. -Daniel > > > > + if (current_pclk == intel_dsi->pclk) { > > + config->dsi_pll.ctrl &= DSI_PLL_P1_POST_DIV_MASK; > > + } else { > > + dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, > > + intel_dsi->pixel_format, > > + intel_dsi->lane_count); > > + > > + ret = dsi_calc_mnp(dev_priv, config, dsi_clk); > > + if (ret) { > > + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); > > + return ret; > > + } > > } > > > > if (intel_dsi->ports & (1 << PORT_A)) > > -- > > 2.23.0 > > -- > Ville Syrjälä > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-11-07 11:37 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-10-20 18:21 [PATCH] drm/i915: Try to re-use GOP / previous M-N-P settings for vlv DSI PLL Hans de Goede 2019-10-20 19:10 ` ✓ Fi.CI.BAT: success for " Patchwork 2019-10-20 21:23 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-07 11:24 ` [PATCH] " Ville Syrjälä 2019-11-07 11:24 ` [Intel-gfx] " Ville Syrjälä 2019-11-07 11:24 ` Ville Syrjälä 2019-11-07 11:37 ` Daniel Vetter 2019-11-07 11:37 ` [Intel-gfx] " Daniel Vetter 2019-11-07 11:37 ` Daniel Vetter
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