From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
jbrunet@baylibre.com, khilman@baylibre.com,
linux-amlogic@lists.infradead.org, narmstrong@baylibre.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Rob Herring <robh@kernel.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Date: Fri, 08 Nov 2019 14:07:16 -0800 [thread overview]
Message-ID: <20191108220717.150422084D@mail.kernel.org> (raw)
In-Reply-To: <20191027162328.1177402-2-martin.blumenstingl@googlemail.com>
Quoting Martin Blumenstingl (2019-10-27 09:23:24)
> Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in
> the MMCBUS registers. There is no public documentation on this, but the
> GPL u-boot sources from the Amlogic BSP show that:
> - it uses the same XTAL input as the main clock controller
> - it contains a PLL which seems to be implemented just like the other
> PLLs in this SoC
> - there is a power-of-two PLL post-divider
>
> Add the documentation and header file for this DDR clock controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
jbrunet@baylibre.com, khilman@baylibre.com,
linux-amlogic@lists.infradead.org, narmstrong@baylibre.com
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Date: Fri, 08 Nov 2019 14:07:16 -0800 [thread overview]
Message-ID: <20191108220717.150422084D@mail.kernel.org> (raw)
In-Reply-To: <20191027162328.1177402-2-martin.blumenstingl@googlemail.com>
Quoting Martin Blumenstingl (2019-10-27 09:23:24)
> Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in
> the MMCBUS registers. There is no public documentation on this, but the
> GPL u-boot sources from the Amlogic BSP show that:
> - it uses the same XTAL input as the main clock controller
> - it contains a PLL which seems to be implemented just like the other
> PLLs in this SoC
> - there is a power-of-two PLL post-divider
>
> Add the documentation and header file for this DDR clock controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
jbrunet@baylibre.com, khilman@baylibre.com,
linux-amlogic@lists.infradead.org, narmstrong@baylibre.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Rob Herring <robh@kernel.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Date: Fri, 08 Nov 2019 14:07:16 -0800 [thread overview]
Message-ID: <20191108220717.150422084D@mail.kernel.org> (raw)
In-Reply-To: <20191027162328.1177402-2-martin.blumenstingl@googlemail.com>
Quoting Martin Blumenstingl (2019-10-27 09:23:24)
> Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in
> the MMCBUS registers. There is no public documentation on this, but the
> GPL u-boot sources from the Amlogic BSP show that:
> - it uses the same XTAL input as the main clock controller
> - it contains a PLL which seems to be implemented just like the other
> PLLs in this SoC
> - there is a power-of-two PLL post-divider
>
> Add the documentation and header file for this DDR clock controller.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-08 22:07 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-27 16:23 [PATCH v2 0/5] add the DDR clock controller on Meson8 and Meson8b Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-11-08 22:07 ` Stephen Boyd [this message]
2019-11-08 22:07 ` Stephen Boyd
2019-11-08 22:07 ` Stephen Boyd
2019-10-27 16:23 ` [PATCH v2 2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-11-08 22:16 ` Stephen Boyd
2019-11-08 22:16 ` Stephen Boyd
2019-11-08 22:16 ` Stephen Boyd
2019-11-12 17:20 ` Jerome Brunet
2019-11-12 17:20 ` Jerome Brunet
2019-11-12 17:20 ` Jerome Brunet
2019-11-12 20:52 ` Martin Blumenstingl
2019-11-12 20:52 ` Martin Blumenstingl
2019-11-12 20:52 ` Martin Blumenstingl
2019-11-16 16:52 ` Martin Blumenstingl
2019-11-16 16:52 ` Martin Blumenstingl
2019-11-16 16:52 ` Martin Blumenstingl
2019-10-27 16:23 ` [PATCH v2 3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-11-08 22:07 ` Stephen Boyd
2019-11-08 22:07 ` Stephen Boyd
2019-11-08 22:07 ` Stephen Boyd
2019-10-27 16:23 ` [PATCH v2 4/5] ARM: dts: meson8: add the DDR clock controller Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` [PATCH v2 5/5] ARM: dts: meson8b: " Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
2019-10-27 16:23 ` Martin Blumenstingl
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