* [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
amdgpu and radeon do a bit of mucking with the PCIe Link Control 2
register, some of it using hard-coded magic numbers. The idea here is to
replace those with #defines.
Since v2:
- Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
- Separate out the functional changes for better bisection (thanks,
Michel!)
- Add #defines in a patch by themselves (so a GPU revert wouldn't break
other potential users)
- Squash all the magic number -> #define changes into one patch
Since v1:
- Add my signed-off-by and Alex's reviewed-by.
Bjorn Helgaas (3):
PCI: Add #defines for Enter Compliance, Transmit Margin
drm: correct Transmit Margin masks
drm: replace numbers with PCI_EXP_LNKCTL2 definitions
drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
include/uapi/linux/pci_regs.h | 2 ++
5 files changed, 58 insertions(+), 32 deletions(-)
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas, Ilia Mirkin
From: Bjorn Helgaas <bhelgaas@google.com>
amdgpu and radeon do a bit of mucking with the PCIe Link Control 2
register, some of it using hard-coded magic numbers. The idea here is to
replace those with #defines.
Since v2:
- Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
- Separate out the functional changes for better bisection (thanks,
Michel!)
- Add #defines in a patch by themselves (so a GPU revert wouldn't break
other potential users)
- Squash all the magic number -> #define changes into one patch
Since v1:
- Add my signed-off-by and Alex's reviewed-by.
Bjorn Helgaas (3):
PCI: Add #defines for Enter Compliance, Transmit Margin
drm: correct Transmit Margin masks
drm: replace numbers with PCI_EXP_LNKCTL2 definitions
drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
include/uapi/linux/pci_regs.h | 2 ++
5 files changed, 58 insertions(+), 32 deletions(-)
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread[parent not found: <20191112173503.176611-1-helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]
* [PATCH 1/3] PCI: Add #defines for Enter Compliance, Transmit Margin
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci-u79uwXL29TY76Z2rM5mHXA,
Michel Dänzer, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Bjorn Helgaas,
Ilia Mirkin
From: Bjorn Helgaas <bhelgaas@google.com>
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 29d6e93fd15e..5869e5778a05 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/3] PCI: Add #defines for Enter Compliance, Transmit Margin
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 29d6e93fd15e..5869e5778a05 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/3] PCI: Add #defines for Enter Compliance, Transmit Margin
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, amd-gfx, dri-devel, linux-kernel, Ilia Mirkin,
linux-pci, Michel Dänzer, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 29d6e93fd15e..5869e5778a05 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
--
2.24.0.rc1.363.gb1bccd3e3d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/3] PCI: Add #defines for Enter Compliance, Transmit Margin
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas, Ilia Mirkin
From: Bjorn Helgaas <bhelgaas@google.com>
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
include/uapi/linux/pci_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 29d6e93fd15e..5869e5778a05 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -673,6 +673,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/3] drm: correct Transmit Margin masks
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
drivers/gpu/drm/radeon/cik.c | 8 ++++----
drivers/gpu/drm/radeon/si.c | 8 ++++----
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 62eab82a64f9..14cdfdf78bde 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 05894d198a79..9b7042d3ef1b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/3] drm: correct Transmit Margin masks
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, amd-gfx, dri-devel, linux-kernel, Ilia Mirkin,
linux-pci, Michel Dänzer, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
drivers/gpu/drm/radeon/cik.c | 8 ++++----
drivers/gpu/drm/radeon/si.c | 8 ++++----
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 62eab82a64f9..14cdfdf78bde 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 05894d198a79..9b7042d3ef1b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/3] drm: correct Transmit Margin masks
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas, Ilia Mirkin
From: Bjorn Helgaas <bhelgaas@google.com>
Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.
Correct the mask to "7 << 7", which is the Transmit Margin field.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++----
drivers/gpu/drm/radeon/cik.c | 8 ++++----
drivers/gpu/drm/radeon/si.c | 8 ++++----
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..13a5696d2a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f2..1e350172dc7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 62eab82a64f9..14cdfdf78bde 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 05894d198a79..9b7042d3ef1b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 9));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+ tmp16 &= ~((1 << 4) | (7 << 7));
+ tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/3] drm: replace numbers with PCI_EXP_LNKCTL2 definitions
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, amd-gfx, dri-devel, linux-kernel, Ilia Mirkin,
linux-pci, Michel Dänzer, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 13a5696d2a6a..3067bb874032 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
@@ -1521,13 +1527,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1e350172dc7b..a7dcb0d0f039 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -1758,13 +1764,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 14cdfdf78bde..a280442c81aa 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -9641,13 +9647,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 9b7042d3ef1b..529e70a42019 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -7224,13 +7230,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/3] drm: replace numbers with PCI_EXP_LNKCTL2 definitions
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas
From: Bjorn Helgaas <bhelgaas@google.com>
Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 13a5696d2a6a..3067bb874032 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
@@ -1521,13 +1527,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1e350172dc7b..a7dcb0d0f039 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -1758,13 +1764,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 14cdfdf78bde..a280442c81aa 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -9641,13 +9647,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 9b7042d3ef1b..529e70a42019 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -7224,13 +7230,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/3] drm: replace numbers with PCI_EXP_LNKCTL2 definitions
@ 2019-11-12 17:35 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 17:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Zhou, David Airlie,
Daniel Vetter
Cc: Frederick Lawler, linux-pci, Michel Dänzer, linux-kernel,
dri-devel, amd-gfx, Bjorn Helgaas, Ilia Mirkin
From: Bjorn Helgaas <bhelgaas@google.com>
Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 13a5696d2a6a..3067bb874032 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
@@ -1521,13 +1527,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1e350172dc7b..a7dcb0d0f039 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -1758,13 +1764,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- tmp16 |= 3;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- tmp16 |= 2;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1;
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 14cdfdf78bde..a280442c81aa 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -9641,13 +9647,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 9b7042d3ef1b..529e70a42019 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
/* linkctl2 */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (bridge_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~((1 << 4) | (7 << 7));
- tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN);
+ tmp16 |= (gpu_cfg2 &
+ (PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN));
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -7224,13 +7230,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- tmp16 &= ~0xf;
+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
if (speed_cap == PCIE_SPEED_8_0GT)
- tmp16 |= 3; /* gen3 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
else if (speed_cap == PCIE_SPEED_5_0GT)
- tmp16 |= 2; /* gen2 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
else
- tmp16 |= 1; /* gen1 */
+ tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
--
2.24.0.rc1.363.gb1bccd3e3d-goog
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* RE: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 19:35 ` Deucher, Alexander
0 siblings, 0 replies; 19+ messages in thread
From: Deucher, Alexander @ 2019-11-12 19:35 UTC (permalink / raw)
To: Bjorn Helgaas, Koenig, Christian, Zhou, David(ChunMing),
David Airlie, Daniel Vetter
Cc: Frederick Lawler, linux-pci@vger.kernel.org, Michel Dänzer,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org, Bjorn Helgaas
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Bjorn Helgaas
> Sent: Tuesday, November 12, 2019 12:35 PM
> To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>
> Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> Subject: [PATCH V3 0/3] drm: replace magic numbers
>
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> some of it using hard-coded magic numbers. The idea here is to replace
> those with #defines.
>
> Since v2:
> - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> - Separate out the functional changes for better bisection (thanks,
> Michel!)
> - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> other potential users)
> - Squash all the magic number -> #define changes into one patch
>
> Since v1:
> - Add my signed-off-by and Alex's reviewed-by.
>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I'm happy to have it go through whatever tree is easiest for you.
Thanks,
Alex
> Bjorn Helgaas (3):
> PCI: Add #defines for Enter Compliance, Transmit Margin
> drm: correct Transmit Margin masks
> drm: replace numbers with PCI_EXP_LNKCTL2 definitions
>
> drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> include/uapi/linux/pci_regs.h | 2 ++
> 5 files changed, 58 insertions(+), 32 deletions(-)
>
> --
> 2.24.0.rc1.363.gb1bccd3e3d-goog
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 19:35 ` Deucher, Alexander
0 siblings, 0 replies; 19+ messages in thread
From: Deucher, Alexander @ 2019-11-12 19:35 UTC (permalink / raw)
To: Bjorn Helgaas, Koenig, Christian, Zhou, David(ChunMing),
David Airlie, Daniel Vetter
Cc: Frederick Lawler, linux-pci@vger.kernel.org, Michel Dänzer,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org, Bjorn Helgaas, Ilia Mirkin
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Bjorn Helgaas
> Sent: Tuesday, November 12, 2019 12:35 PM
> To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>
> Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> Subject: [PATCH V3 0/3] drm: replace magic numbers
>
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> some of it using hard-coded magic numbers. The idea here is to replace
> those with #defines.
>
> Since v2:
> - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> - Separate out the functional changes for better bisection (thanks,
> Michel!)
> - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> other potential users)
> - Squash all the magic number -> #define changes into one patch
>
> Since v1:
> - Add my signed-off-by and Alex's reviewed-by.
>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I'm happy to have it go through whatever tree is easiest for you.
Thanks,
Alex
> Bjorn Helgaas (3):
> PCI: Add #defines for Enter Compliance, Transmit Margin
> drm: correct Transmit Margin masks
> drm: replace numbers with PCI_EXP_LNKCTL2 definitions
>
> drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> include/uapi/linux/pci_regs.h | 2 ++
> 5 files changed, 58 insertions(+), 32 deletions(-)
>
> --
> 2.24.0.rc1.363.gb1bccd3e3d-goog
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 19:35 ` Deucher, Alexander
0 siblings, 0 replies; 19+ messages in thread
From: Deucher, Alexander @ 2019-11-12 19:35 UTC (permalink / raw)
To: Bjorn Helgaas, Koenig, Christian, Zhou, David(ChunMing),
David Airlie, Daniel Vetter
Cc: Frederick Lawler, linux-pci@vger.kernel.org, Michel Dänzer,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org, Bjorn Helgaas, Ilia Mirkin
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Bjorn Helgaas
> Sent: Tuesday, November 12, 2019 12:35 PM
> To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>
> Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> Subject: [PATCH V3 0/3] drm: replace magic numbers
>
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> some of it using hard-coded magic numbers. The idea here is to replace
> those with #defines.
>
> Since v2:
> - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> - Separate out the functional changes for better bisection (thanks,
> Michel!)
> - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> other potential users)
> - Squash all the magic number -> #define changes into one patch
>
> Since v1:
> - Add my signed-off-by and Alex's reviewed-by.
>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I'm happy to have it go through whatever tree is easiest for you.
Thanks,
Alex
> Bjorn Helgaas (3):
> PCI: Add #defines for Enter Compliance, Transmit Margin
> drm: correct Transmit Margin masks
> drm: replace numbers with PCI_EXP_LNKCTL2 definitions
>
> drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> include/uapi/linux/pci_regs.h | 2 ++
> 5 files changed, 58 insertions(+), 32 deletions(-)
>
> --
> 2.24.0.rc1.363.gb1bccd3e3d-goog
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 21:52 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 21:52 UTC (permalink / raw)
To: Deucher, Alexander
Cc: Koenig, Christian, Zhou, David(ChunMing), David Airlie,
Daniel Vetter, Frederick Lawler, linux-pci@vger.kernel.org,
Michel Dänzer, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
Ilia Mirkin
On Tue, Nov 12, 2019 at 07:35:53PM +0000, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Bjorn Helgaas
> > Sent: Tuesday, November 12, 2019 12:35 PM
> > To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> > <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> > <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> > <daniel@ffwll.ch>
> > Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> > Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> > devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> > <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> > Subject: [PATCH V3 0/3] drm: replace magic numbers
> >
> > From: Bjorn Helgaas <bhelgaas@google.com>
> >
> > amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> > some of it using hard-coded magic numbers. The idea here is to replace
> > those with #defines.
> >
> > Since v2:
> > - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> > - Separate out the functional changes for better bisection (thanks,
> > Michel!)
> > - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> > other potential users)
> > - Squash all the magic number -> #define changes into one patch
> >
> > Since v1:
> > - Add my signed-off-by and Alex's reviewed-by.
> >
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> I'm happy to have it go through whatever tree is easiest for you.
OK, thanks! I applied your reviewed-by and put these on my pci/misc
branch for v5.5, in hopes that we might get a followup patch from Fred
along the lines of 6133b9204c0a ("cxgb4: Prefer
pcie_capability_read_word()")
> > Bjorn Helgaas (3):
> > PCI: Add #defines for Enter Compliance, Transmit Margin
> > drm: correct Transmit Margin masks
> > drm: replace numbers with PCI_EXP_LNKCTL2 definitions
> >
> > drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> > include/uapi/linux/pci_regs.h | 2 ++
> > 5 files changed, 58 insertions(+), 32 deletions(-)
> >
> > --
> > 2.24.0.rc1.363.gb1bccd3e3d-goog
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 21:52 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 21:52 UTC (permalink / raw)
To: Deucher, Alexander
Cc: Frederick Lawler, David Airlie, linux-pci@vger.kernel.org,
Michel Dänzer, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
Koenig, Christian
On Tue, Nov 12, 2019 at 07:35:53PM +0000, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Bjorn Helgaas
> > Sent: Tuesday, November 12, 2019 12:35 PM
> > To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> > <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> > <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> > <daniel@ffwll.ch>
> > Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> > Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> > devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> > <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> > Subject: [PATCH V3 0/3] drm: replace magic numbers
> >
> > From: Bjorn Helgaas <bhelgaas@google.com>
> >
> > amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> > some of it using hard-coded magic numbers. The idea here is to replace
> > those with #defines.
> >
> > Since v2:
> > - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> > - Separate out the functional changes for better bisection (thanks,
> > Michel!)
> > - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> > other potential users)
> > - Squash all the magic number -> #define changes into one patch
> >
> > Since v1:
> > - Add my signed-off-by and Alex's reviewed-by.
> >
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> I'm happy to have it go through whatever tree is easiest for you.
OK, thanks! I applied your reviewed-by and put these on my pci/misc
branch for v5.5, in hopes that we might get a followup patch from Fred
along the lines of 6133b9204c0a ("cxgb4: Prefer
pcie_capability_read_word()")
> > Bjorn Helgaas (3):
> > PCI: Add #defines for Enter Compliance, Transmit Margin
> > drm: correct Transmit Margin masks
> > drm: replace numbers with PCI_EXP_LNKCTL2 definitions
> >
> > drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> > include/uapi/linux/pci_regs.h | 2 ++
> > 5 files changed, 58 insertions(+), 32 deletions(-)
> >
> > --
> > 2.24.0.rc1.363.gb1bccd3e3d-goog
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH V3 0/3] drm: replace magic numbers
@ 2019-11-12 21:52 ` Bjorn Helgaas
0 siblings, 0 replies; 19+ messages in thread
From: Bjorn Helgaas @ 2019-11-12 21:52 UTC (permalink / raw)
To: Deucher, Alexander
Cc: Zhou, David(ChunMing), Frederick Lawler, David Airlie,
linux-pci@vger.kernel.org, Michel Dänzer,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org, Daniel Vetter, Koenig, Christian,
Ilia Mirkin
On Tue, Nov 12, 2019 at 07:35:53PM +0000, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Bjorn Helgaas
> > Sent: Tuesday, November 12, 2019 12:35 PM
> > To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian
> > <Christian.Koenig@amd.com>; Zhou, David(ChunMing)
> > <David1.Zhou@amd.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> > <daniel@ffwll.ch>
> > Cc: Frederick Lawler <fred@fredlawl.com>; linux-pci@vger.kernel.org;
> > Michel Dänzer <michel@daenzer.net>; linux-kernel@vger.kernel.org; dri-
> > devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> > <bhelgaas@google.com>; Ilia Mirkin <imirkin@alum.mit.edu>
> > Subject: [PATCH V3 0/3] drm: replace magic numbers
> >
> > From: Bjorn Helgaas <bhelgaas@google.com>
> >
> > amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> > some of it using hard-coded magic numbers. The idea here is to replace
> > those with #defines.
> >
> > Since v2:
> > - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> > - Separate out the functional changes for better bisection (thanks,
> > Michel!)
> > - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> > other potential users)
> > - Squash all the magic number -> #define changes into one patch
> >
> > Since v1:
> > - Add my signed-off-by and Alex's reviewed-by.
> >
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> I'm happy to have it go through whatever tree is easiest for you.
OK, thanks! I applied your reviewed-by and put these on my pci/misc
branch for v5.5, in hopes that we might get a followup patch from Fred
along the lines of 6133b9204c0a ("cxgb4: Prefer
pcie_capability_read_word()")
> > Bjorn Helgaas (3):
> > PCI: Add #defines for Enter Compliance, Transmit Margin
> > drm: correct Transmit Margin masks
> > drm: replace numbers with PCI_EXP_LNKCTL2 definitions
> >
> > drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++--------
> > drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++--------
> > include/uapi/linux/pci_regs.h | 2 ++
> > 5 files changed, 58 insertions(+), 32 deletions(-)
> >
> > --
> > 2.24.0.rc1.363.gb1bccd3e3d-goog
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread