* [Intel-gfx] [PATCH 00/10] drm/i915: Cleanups around .crtc_enable/disable()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
My eyes have been bleeding long enough. Let's try to clean up some of
this mess.
Ville Syrjälä (10):
drm/i915: Change intel_encoders_<hook>() calling convention
drm/i915: Add intel_crtc_vblank_off()
drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
drm/i915: Move crtc_state to tighter scope
drm/i915: Pass intel_crtc to ironlake_fdi_disable()
drm/i915: Change watermark hook calling convention
drm/i915: Pass dev_priv to cpt_verify_modeset()
drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
drm/i915: Change .crtc_enable/disable() calling convention
drivers/gpu/drm/i915/display/intel_display.c | 461 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +--
3 files changed, 272 insertions(+), 266 deletions(-)
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state and the crtc to intel_encoders_enable() & co.
Make life simpler when you don't have to think which state (old vs. new)
you have to pass in. Also constify the states while at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f3340554149..da01fa6928a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6299,11 +6299,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
}
}
-static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6319,11 +6320,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_pre_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6339,11 +6341,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6360,11 +6363,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6381,11 +6385,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6401,11 +6406,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6421,11 +6427,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_update_pipe(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_update_pipe(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6492,7 +6499,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6525,7 +6532,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6596,12 +6603,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6679,7 +6686,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6727,7 +6734,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6739,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (old_crtc_state->has_pch_encoder)
ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6777,7 +6784,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6802,9 +6809,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7035,7 +7042,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, pipe_config);
@@ -7045,7 +7052,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
vlv_enable_pll(intel_crtc, pipe_config);
}
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_pfit_enable(pipe_config);
@@ -7060,7 +7067,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7099,7 +7106,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_enable_pll(intel_crtc, pipe_config);
@@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7154,7 +7161,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -7163,7 +7170,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7174,7 +7181,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -14340,7 +14347,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_pre_plane_update(old_crtc_state, new_crtc_state);
if (new_crtc_state->update_pipe)
- intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ intel_encoders_update_pipe(state, crtc);
}
if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state and the crtc to intel_encoders_enable() & co.
Make life simpler when you don't have to think which state (old vs. new)
you have to pass in. Also constify the states while at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f3340554149..da01fa6928a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6299,11 +6299,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
}
}
-static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6319,11 +6320,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_pre_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6339,11 +6341,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6360,11 +6363,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6381,11 +6385,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6401,11 +6406,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6421,11 +6427,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_update_pipe(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_update_pipe(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6492,7 +6499,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6525,7 +6532,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6596,12 +6603,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6679,7 +6686,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6727,7 +6734,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6739,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (old_crtc_state->has_pch_encoder)
ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6777,7 +6784,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6802,9 +6809,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7035,7 +7042,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, pipe_config);
@@ -7045,7 +7052,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
vlv_enable_pll(intel_crtc, pipe_config);
}
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_pfit_enable(pipe_config);
@@ -7060,7 +7067,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7099,7 +7106,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_enable_pll(intel_crtc, pipe_config);
@@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7154,7 +7161,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -7163,7 +7170,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7174,7 +7181,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -14340,7 +14347,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_pre_plane_update(old_crtc_state, new_crtc_state);
if (new_crtc_state->update_pipe)
- intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ intel_encoders_update_pipe(state, crtc);
}
if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-13 23:48 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-13 23:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:54PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic state and the crtc to intel_encoders_enable() & co.
> Make life simpler when you don't have to think which state (old vs. new)
> you have to pass in. Also constify the states while at it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Oh thank you for making life around the encoder functions easier
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
> 1 file changed, 54 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5f3340554149..da01fa6928a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6299,11 +6299,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
> }
> }
>
> -static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6319,11 +6320,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_pre_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_pre_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6339,11 +6341,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6360,11 +6363,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6381,11 +6385,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_post_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_post_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6401,11 +6406,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6421,11 +6427,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_update_pipe(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_update_pipe(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6492,7 +6499,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc->active = true;
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> if (pipe_config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -6525,7 +6532,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev, intel_crtc->pipe);
> @@ -6596,12 +6603,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (WARN_ON(intel_crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_pll_enable(state, intel_crtc);
>
> if (pipe_config->shared_dpll)
> intel_enable_shared_dpll(pipe_config);
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
> @@ -6679,7 +6686,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
>
> if (psl_clkgate_wa) {
> intel_wait_for_vblank(dev_priv, pipe);
> @@ -6727,7 +6734,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -6739,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (old_crtc_state->has_pch_encoder)
> ironlake_fdi_disable(crtc);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> if (old_crtc_state->has_pch_encoder) {
> ironlake_disable_pch_transcoder(dev_priv, pipe);
> @@ -6777,7 +6784,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -6802,9 +6809,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> else
> ironlake_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_pll_disable(state, intel_crtc);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -7035,7 +7042,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_pll_enable(state, intel_crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> chv_prepare_pll(intel_crtc, pipe_config);
> @@ -7045,7 +7052,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> vlv_enable_pll(intel_crtc, pipe_config);
> }
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7060,7 +7067,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
> }
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> @@ -7099,7 +7106,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> i9xx_enable_pll(intel_crtc, pipe_config);
>
> @@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
> }
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -7154,7 +7161,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (IS_GEN(dev_priv, 2))
> intel_wait_for_vblank(dev_priv, pipe);
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -7163,7 +7170,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> i9xx_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev_priv))
> @@ -7174,7 +7181,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> i9xx_disable_pll(old_crtc_state);
> }
>
> - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_pll_disable(state, intel_crtc);
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> @@ -14340,7 +14347,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> intel_pre_plane_update(old_crtc_state, new_crtc_state);
>
> if (new_crtc_state->update_pipe)
> - intel_encoders_update_pipe(crtc, new_crtc_state, state);
> + intel_encoders_update_pipe(state, crtc);
> }
>
> if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-13 23:48 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-13 23:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:54PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic state and the crtc to intel_encoders_enable() & co.
> Make life simpler when you don't have to think which state (old vs. new)
> you have to pass in. Also constify the states while at it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Oh thank you for making life around the encoder functions easier
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
> 1 file changed, 54 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5f3340554149..da01fa6928a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6299,11 +6299,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
> }
> }
>
> -static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6319,11 +6320,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_pre_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_pre_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6339,11 +6341,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_enable(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6360,11 +6363,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6381,11 +6385,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_post_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_post_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6401,11 +6406,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
> - struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *old_conn_state;
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + const struct drm_connector_state *old_conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6421,11 +6427,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
> }
> }
>
> -static void intel_encoders_update_pipe(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state,
> - struct intel_atomic_state *state)
> +static void intel_encoders_update_pipe(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct drm_connector_state *conn_state;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> int i;
>
> @@ -6492,7 +6499,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc->active = true;
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> if (pipe_config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -6525,7 +6532,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev, intel_crtc->pipe);
> @@ -6596,12 +6603,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (WARN_ON(intel_crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_pll_enable(state, intel_crtc);
>
> if (pipe_config->shared_dpll)
> intel_enable_shared_dpll(pipe_config);
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
> @@ -6679,7 +6686,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
>
> if (psl_clkgate_wa) {
> intel_wait_for_vblank(dev_priv, pipe);
> @@ -6727,7 +6734,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -6739,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (old_crtc_state->has_pch_encoder)
> ironlake_fdi_disable(crtc);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> if (old_crtc_state->has_pch_encoder) {
> ironlake_disable_pch_transcoder(dev_priv, pipe);
> @@ -6777,7 +6784,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -6802,9 +6809,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> else
> ironlake_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_pll_disable(state, intel_crtc);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -7035,7 +7042,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_pll_enable(state, intel_crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> chv_prepare_pll(intel_crtc, pipe_config);
> @@ -7045,7 +7052,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> vlv_enable_pll(intel_crtc, pipe_config);
> }
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7060,7 +7067,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
> }
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> @@ -7099,7 +7106,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> + intel_encoders_pre_enable(state, intel_crtc);
>
> i9xx_enable_pll(intel_crtc, pipe_config);
>
> @@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(intel_crtc, pipe_config, state);
> + intel_encoders_enable(state, intel_crtc);
> }
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -7154,7 +7161,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (IS_GEN(dev_priv, 2))
> intel_wait_for_vblank(dev_priv, pipe);
>
> - intel_encoders_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_disable(state, intel_crtc);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -7163,7 +7170,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> i9xx_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_disable(state, intel_crtc);
>
> if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev_priv))
> @@ -7174,7 +7181,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> i9xx_disable_pll(old_crtc_state);
> }
>
> - intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> + intel_encoders_post_pll_disable(state, intel_crtc);
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> @@ -14340,7 +14347,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> intel_pre_plane_update(old_crtc_state, new_crtc_state);
>
> if (new_crtc_state->update_pipe)
> - intel_encoders_update_pipe(crtc, new_crtc_state, state);
> + intel_encoders_update_pipe(state, crtc);
> }
>
> if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have intel_crtc_vblank_on(). Add a counterpart so we
don't have to inline the disable+assert all over.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da01fa6928a2..194029ff8617 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1831,6 +1831,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
drm_crtc_vblank_on(&crtc->base);
}
+static void intel_crtc_vblank_off(struct intel_crtc *crtc)
+{
+ drm_crtc_vblank_off(&crtc->base);
+ assert_vblank_disabled(&crtc->base);
+}
+
static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -6736,8 +6742,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
@@ -6786,8 +6791,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -7163,8 +7167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have intel_crtc_vblank_on(). Add a counterpart so we
don't have to inline the disable+assert all over.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da01fa6928a2..194029ff8617 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1831,6 +1831,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
drm_crtc_vblank_on(&crtc->base);
}
+static void intel_crtc_vblank_off(struct intel_crtc *crtc)
+{
+ drm_crtc_vblank_off(&crtc->base);
+ assert_vblank_disabled(&crtc->base);
+}
+
static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -6736,8 +6742,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
@@ -6786,8 +6791,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -7163,8 +7167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-13 23:50 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-13 23:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:55PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already have intel_crtc_vblank_on(). Add a counterpart so we
> don't have to inline the disable+assert all over.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index da01fa6928a2..194029ff8617 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1831,6 +1831,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> drm_crtc_vblank_on(&crtc->base);
> }
>
> +static void intel_crtc_vblank_off(struct intel_crtc *crtc)
> +{
> + drm_crtc_vblank_off(&crtc->base);
> + assert_vblank_disabled(&crtc->base);
> +}
> +
> static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> @@ -6736,8 +6742,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> @@ -6786,8 +6791,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -7163,8 +7167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-13 23:50 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-13 23:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:55PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already have intel_crtc_vblank_on(). Add a counterpart so we
> don't have to inline the disable+assert all over.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
LGTM,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index da01fa6928a2..194029ff8617 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1831,6 +1831,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> drm_crtc_vblank_on(&crtc->base);
> }
>
> +static void intel_crtc_vblank_off(struct intel_crtc *crtc)
> +{
> + drm_crtc_vblank_off(&crtc->base);
> + assert_vblank_disabled(&crtc->base);
> +}
> +
> static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> @@ -6736,8 +6742,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> @@ -6786,8 +6791,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -7163,8 +7167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_disable(state, intel_crtc);
>
> - drm_crtc_vblank_off(crtc);
> - assert_vblank_disabled(crtc);
> + intel_crtc_vblank_off(intel_crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the assert_vblank_disabled() into intel_crtc_vblank_on()
so that we don't have to inline it all over.
This does mean we now assert_vblank_disabled() during readout as well
but that is totally fine as it happens after drm_crtc_vblank_reset().
One can even argue it's what we want to do anyway to make sure
the reset actually happened.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 194029ff8617..89d150b45520 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1826,6 +1826,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ assert_vblank_disabled(&crtc->base);
drm_crtc_set_max_vblank_count(&crtc->base,
intel_crtc_max_vblank_count(crtc_state));
drm_crtc_vblank_on(&crtc->base);
@@ -6535,7 +6536,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
ironlake_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -6689,7 +6689,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(pipe_config, true);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7068,7 +7067,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7128,7 +7126,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the assert_vblank_disabled() into intel_crtc_vblank_on()
so that we don't have to inline it all over.
This does mean we now assert_vblank_disabled() during readout as well
but that is totally fine as it happens after drm_crtc_vblank_reset().
One can even argue it's what we want to do anyway to make sure
the reset actually happened.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 194029ff8617..89d150b45520 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1826,6 +1826,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ assert_vblank_disabled(&crtc->base);
drm_crtc_set_max_vblank_count(&crtc->base,
intel_crtc_max_vblank_count(crtc_state));
drm_crtc_vblank_on(&crtc->base);
@@ -6535,7 +6536,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
ironlake_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -6689,7 +6689,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(pipe_config, true);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7068,7 +7067,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7128,7 +7126,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-14 0:05 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:56PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the assert_vblank_disabled() into intel_crtc_vblank_on()
> so that we don't have to inline it all over.
>
> This does mean we now assert_vblank_disabled() during readout as well
> but that is totally fine as it happens after drm_crtc_vblank_reset().
> One can even argue it's what we want to do anyway to make sure
> the reset actually happened.
Yes this makes total sense to me and double checking with the code
it looks fine to have it during the readout after drm_crtc_vblank_reset()
hence,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 194029ff8617..89d150b45520 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1826,6 +1826,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> + assert_vblank_disabled(&crtc->base);
> drm_crtc_set_max_vblank_count(&crtc->base,
> intel_crtc_max_vblank_count(crtc_state));
> drm_crtc_vblank_on(&crtc->base);
> @@ -6535,7 +6536,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> if (pipe_config->has_pch_encoder)
> ironlake_pch_enable(state, pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -6689,7 +6689,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> intel_ddi_set_vc_payload_alloc(pipe_config, true);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -7068,7 +7067,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> dev_priv->display.initial_watermarks(state, pipe_config);
> intel_enable_pipe(pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -7128,7 +7126,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_update_watermarks(intel_crtc);
> intel_enable_pipe(pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-14 0:05 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:56PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the assert_vblank_disabled() into intel_crtc_vblank_on()
> so that we don't have to inline it all over.
>
> This does mean we now assert_vblank_disabled() during readout as well
> but that is totally fine as it happens after drm_crtc_vblank_reset().
> One can even argue it's what we want to do anyway to make sure
> the reset actually happened.
Yes this makes total sense to me and double checking with the code
it looks fine to have it during the readout after drm_crtc_vblank_reset()
hence,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 194029ff8617..89d150b45520 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1826,6 +1826,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> + assert_vblank_disabled(&crtc->base);
> drm_crtc_set_max_vblank_count(&crtc->base,
> intel_crtc_max_vblank_count(crtc_state));
> drm_crtc_vblank_on(&crtc->base);
> @@ -6535,7 +6536,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> if (pipe_config->has_pch_encoder)
> ironlake_pch_enable(state, pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -6689,7 +6689,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> intel_ddi_set_vc_payload_alloc(pipe_config, true);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -7068,7 +7067,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> dev_priv->display.initial_watermarks(state, pipe_config);
> intel_enable_pipe(pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> @@ -7128,7 +7126,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_update_watermarks(intel_crtc);
> intel_enable_pipe(pipe_config);
>
> - assert_vblank_disabled(crtc);
> intel_crtc_vblank_on(pipe_config);
>
> intel_encoders_enable(state, intel_crtc);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_modeset_setup_hw_state() doesn't need the crtc_state at the
top level scope. Move it to where it's needed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89d150b45520..e52ea9643790 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17716,7 +17716,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_state *crtc_state;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
@@ -17749,7 +17748,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
* waits, so we need vblank interrupts restored beforehand.
*/
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
drm_crtc_vblank_reset(&crtc->base);
@@ -17763,7 +17763,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_sanitize_encoder(encoder);
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
intel_sanitize_crtc(crtc, ctx);
intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
}
@@ -17796,9 +17798,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
u64 put_domains;
- crtc_state = to_intel_crtc_state(crtc->base.state);
put_domains = modeset_get_crtc_power_domains(crtc_state);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_modeset_setup_hw_state() doesn't need the crtc_state at the
top level scope. Move it to where it's needed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89d150b45520..e52ea9643790 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17716,7 +17716,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_state *crtc_state;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
@@ -17749,7 +17748,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
* waits, so we need vblank interrupts restored beforehand.
*/
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
drm_crtc_vblank_reset(&crtc->base);
@@ -17763,7 +17763,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_sanitize_encoder(encoder);
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
intel_sanitize_crtc(crtc, ctx);
intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
}
@@ -17796,9 +17798,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
u64 put_domains;
- crtc_state = to_intel_crtc_state(crtc->base.state);
put_domains = modeset_get_crtc_power_domains(crtc_state);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-14 0:09 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:57PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_modeset_setup_hw_state() doesn't need the crtc_state at the
> top level scope. Move it to where it's needed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good even though it does add to the code size since we need to derive it in
3 different places and might be more in the future.
But logically makes sense to limit its scop to for loops where its needed.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 89d150b45520..e52ea9643790 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17716,7 +17716,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc_state *crtc_state;
> struct intel_encoder *encoder;
> struct intel_crtc *crtc;
> intel_wakeref_t wakeref;
> @@ -17749,7 +17748,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> * waits, so we need vblank interrupts restored beforehand.
> */
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
>
> drm_crtc_vblank_reset(&crtc->base);
>
> @@ -17763,7 +17763,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> intel_sanitize_encoder(encoder);
>
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> intel_sanitize_crtc(crtc, ctx);
> intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
> }
> @@ -17796,9 +17798,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> }
>
> for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> u64 put_domains;
>
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> put_domains = modeset_get_crtc_power_domains(crtc_state);
> if (WARN_ON(put_domains))
> modeset_put_power_domains(dev_priv, put_domains);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-14 0:09 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:57PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_modeset_setup_hw_state() doesn't need the crtc_state at the
> top level scope. Move it to where it's needed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good even though it does add to the code size since we need to derive it in
3 different places and might be more in the future.
But logically makes sense to limit its scop to for loops where its needed.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 89d150b45520..e52ea9643790 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17716,7 +17716,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc_state *crtc_state;
> struct intel_encoder *encoder;
> struct intel_crtc *crtc;
> intel_wakeref_t wakeref;
> @@ -17749,7 +17748,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> * waits, so we need vblank interrupts restored beforehand.
> */
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
>
> drm_crtc_vblank_reset(&crtc->base);
>
> @@ -17763,7 +17763,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> intel_sanitize_encoder(encoder);
>
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> intel_sanitize_crtc(crtc, ctx);
> intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
> }
> @@ -17796,9 +17798,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
> }
>
> for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> u64 put_domains;
>
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> put_domains = modeset_get_crtc_power_domains(crtc_state);
> if (WARN_ON(put_domains))
> modeset_put_power_domains(dev_priv, put_domains);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Switch to intel_crtc from drm_crtc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e52ea9643790..ffadfd90c3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5049,12 +5049,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
udelay(100);
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_disable(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp;
@@ -6748,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_disable(intel_crtc);
intel_encoders_post_disable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Switch to intel_crtc from drm_crtc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e52ea9643790..ffadfd90c3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5049,12 +5049,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
udelay(100);
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_disable(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp;
@@ -6748,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_disable(intel_crtc);
intel_encoders_post_disable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-14 0:10 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:58PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Switch to intel_crtc from drm_crtc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e52ea9643790..ffadfd90c3cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5049,12 +5049,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
> udelay(100);
> }
>
> -static void ironlake_fdi_disable(struct drm_crtc *crtc)
> +static void ironlake_fdi_disable(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> u32 temp;
>
> @@ -6748,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> ironlake_pfit_disable(old_crtc_state);
>
> if (old_crtc_state->has_pch_encoder)
> - ironlake_fdi_disable(crtc);
> + ironlake_fdi_disable(intel_crtc);
>
> intel_encoders_post_disable(state, intel_crtc);
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-14 0:10 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:58PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Switch to intel_crtc from drm_crtc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e52ea9643790..ffadfd90c3cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5049,12 +5049,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
> udelay(100);
> }
>
> -static void ironlake_fdi_disable(struct drm_crtc *crtc)
> +static void ironlake_fdi_disable(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> u32 temp;
>
> @@ -6748,7 +6746,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> ironlake_pfit_disable(old_crtc_state);
>
> if (old_crtc_state->has_pch_encoder)
> - ironlake_fdi_disable(crtc);
> + ironlake_fdi_disable(intel_crtc);
>
> intel_encoders_post_disable(state, intel_crtc);
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
3 files changed, 53 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ffadfd90c3cf..77b739cda053 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(intel_state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(intel_state, crtc);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc);
@@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, pipe_config);
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
@@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
else
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
@@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
@@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
}
if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state,
- new_crtc_state);
+ dev_priv->display.atomic_update_watermarks(state, crtc);
}
static void intel_update_crtc(struct intel_crtc *crtc,
@@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
- new_crtc_state);
+ dev_priv->display.initial_watermarks(state, crtc);
}
static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
@@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state,
- new_crtc_state);
+ dev_priv->display.optimize_watermarks(state, crtc);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc_state);
+ dev_priv->display.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e0f67babe20..00fe4ed4fb96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..b180342f63a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
}
static void g4x_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
int sprite0_start, sprite1_start, fifo_size;
@@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
}
static void vlv_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
}
static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_values *results = &state->wm_results;
if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc_state);
+ skl_atomic_update_crtc_wm(state, crtc);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-12 14:14 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
3 files changed, 53 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ffadfd90c3cf..77b739cda053 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(intel_state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(intel_state, crtc);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc);
@@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, pipe_config);
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
@@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
else
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
@@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
@@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
}
if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state,
- new_crtc_state);
+ dev_priv->display.atomic_update_watermarks(state, crtc);
}
static void intel_update_crtc(struct intel_crtc *crtc,
@@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
- new_crtc_state);
+ dev_priv->display.initial_watermarks(state, crtc);
}
static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
@@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state,
- new_crtc_state);
+ dev_priv->display.optimize_watermarks(state, crtc);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc_state);
+ dev_priv->display.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e0f67babe20..00fe4ed4fb96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..b180342f63a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
}
static void g4x_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
int sprite0_start, sprite1_start, fifo_size;
@@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
}
static void vlv_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
}
static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_values *results = &state->wm_results;
if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc_state);
+ skl_atomic_update_crtc_wm(state, crtc);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-14 0:22 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> time for the caller when it doesn't have to think what to pass.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
> 3 files changed, 53 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ffadfd90c3cf..77b739cda053 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * we'll continue to update watermarks the old way, if flags tell
> * us to.
> */
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(intel_state,
> - pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(intel_state, crtc);
> else if (pipe_config->update_wm_pre)
> intel_update_watermarks(crtc);
> }
> @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
> intel_enable_pipe(pipe_config);
>
> if (pipe_config->has_pch_encoder)
> @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_enable_transcoder_func(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
>
> if (INTEL_GEN(dev_priv) >= 11)
> icl_pipe_mbus_enable(intel_crtc);
> @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + dev_priv->display.initial_watermarks(state, intel_crtc);
Dont we need to make sure initial_watermarks is present or !NULL before calling it
like we do in all other hooks?
Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
either in this patch or another cleanup patch we should change it all to keep either crtc or
intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc
What do you think?
But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
in valleyview_crtc_enable(),
Reviewed-by: Manasi navare <manasi.d.navare@intel.com>
Manasi
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
> @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state,
> - pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
> else
> intel_update_watermarks(intel_crtc);
> intel_enable_pipe(pipe_config);
> @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> bool modeset = needs_modeset(new_crtc_state);
>
> @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> - dev_priv->display.atomic_update_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.atomic_update_watermarks(state, crtc);
> }
>
> static void intel_update_crtc(struct intel_crtc *crtc,
> @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> if (!new_crtc_state->hw.active &&
> !HAS_GMCH(dev_priv) &&
> dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.initial_watermarks(state, crtc);
> }
>
> static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (dev_priv->display.optimize_watermarks)
> - dev_priv->display.optimize_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.optimize_watermarks(state, crtc);
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> /* Write calculated watermark values back */
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> crtc_state->wm.need_postvbl_update = true;
> - dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> + dev_priv->display.optimize_watermarks(intel_state, crtc);
>
> to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e0f67babe20..00fe4ed4fb96 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
> int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> void (*initial_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> void (*optimize_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> void (*update_wm)(struct intel_crtc *crtc);
> int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..b180342f63a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void g4x_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
>
> static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_uncore *uncore = &dev_priv->uncore;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct vlv_fifo_state *fifo_state =
> &crtc_state->wm.vlv.fifo_state;
> int sprite0_start, sprite1_start, fifo_size;
> @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void vlv_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> }
>
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> enum pipe pipe = crtc->pipe;
>
> if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> }
>
> static void skl_initial_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct skl_ddb_values *results = &state->wm_results;
>
> if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> mutex_lock(&dev_priv->wm.wm_mutex);
>
> if (crtc_state->uapi.active_changed)
> - skl_atomic_update_crtc_wm(state, crtc_state);
> + skl_atomic_update_crtc_wm(state, crtc);
>
> mutex_unlock(&dev_priv->wm.wm_mutex);
> }
> @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-14 0:22 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> time for the caller when it doesn't have to think what to pass.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
> 3 files changed, 53 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ffadfd90c3cf..77b739cda053 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * we'll continue to update watermarks the old way, if flags tell
> * us to.
> */
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(intel_state,
> - pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(intel_state, crtc);
> else if (pipe_config->update_wm_pre)
> intel_update_watermarks(crtc);
> }
> @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
> intel_enable_pipe(pipe_config);
>
> if (pipe_config->has_pch_encoder)
> @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_enable_transcoder_func(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
>
> if (INTEL_GEN(dev_priv) >= 11)
> icl_pipe_mbus_enable(intel_crtc);
> @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - dev_priv->display.initial_watermarks(state, pipe_config);
> + dev_priv->display.initial_watermarks(state, intel_crtc);
Dont we need to make sure initial_watermarks is present or !NULL before calling it
like we do in all other hooks?
Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
either in this patch or another cleanup patch we should change it all to keep either crtc or
intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc
What do you think?
But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
in valleyview_crtc_enable(),
Reviewed-by: Manasi navare <manasi.d.navare@intel.com>
Manasi
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
> @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - if (dev_priv->display.initial_watermarks != NULL)
> - dev_priv->display.initial_watermarks(state,
> - pipe_config);
> + if (dev_priv->display.initial_watermarks)
> + dev_priv->display.initial_watermarks(state, intel_crtc);
> else
> intel_update_watermarks(intel_crtc);
> intel_enable_pipe(pipe_config);
> @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> bool modeset = needs_modeset(new_crtc_state);
>
> @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> - dev_priv->display.atomic_update_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.atomic_update_watermarks(state, crtc);
> }
>
> static void intel_update_crtc(struct intel_crtc *crtc,
> @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> if (!new_crtc_state->hw.active &&
> !HAS_GMCH(dev_priv) &&
> dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.initial_watermarks(state, crtc);
> }
>
> static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (dev_priv->display.optimize_watermarks)
> - dev_priv->display.optimize_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.optimize_watermarks(state, crtc);
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> /* Write calculated watermark values back */
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> crtc_state->wm.need_postvbl_update = true;
> - dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> + dev_priv->display.optimize_watermarks(intel_state, crtc);
>
> to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e0f67babe20..00fe4ed4fb96 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
> int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> void (*initial_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> void (*optimize_watermarks)(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state);
> + struct intel_crtc *crtc);
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> void (*update_wm)(struct intel_crtc *crtc);
> int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..b180342f63a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void g4x_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
>
> static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_uncore *uncore = &dev_priv->uncore;
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct vlv_fifo_state *fifo_state =
> &crtc_state->wm.vlv.fifo_state;
> int sprite0_start, sprite1_start, fifo_size;
> @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void vlv_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> }
>
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> enum pipe pipe = crtc->pipe;
>
> if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> }
>
> static void skl_initial_wm(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct skl_ddb_values *results = &state->wm_results;
>
> if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> mutex_lock(&dev_priv->wm.wm_mutex);
>
> if (crtc_state->uapi.active_changed)
> - skl_atomic_update_crtc_wm(state, crtc_state);
> + skl_atomic_update_crtc_wm(state, crtc);
>
> mutex_unlock(&dev_priv->wm.wm_mutex);
> }
> @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> }
>
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> }
>
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> - struct intel_crtc_state *crtc_state)
> + struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-15 15:18 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2019-11-15 15:18 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Nov 13, 2019 at 04:22:28PM -0800, Manasi Navare wrote:
> On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> > time for the caller when it doesn't have to think what to pass.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
> > drivers/gpu/drm/i915/i915_drv.h | 6 +-
> > drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
> > 3 files changed, 53 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index ffadfd90c3cf..77b739cda053 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> > * we'll continue to update watermarks the old way, if flags tell
> > * us to.
> > */
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(intel_state,
> > - pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(intel_state, crtc);
> > else if (pipe_config->update_wm_pre)
> > intel_update_watermarks(crtc);
> > }
> > @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> > intel_enable_pipe(pipe_config);
> >
> > if (pipe_config->has_pch_encoder)
> > @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_ddi_enable_transcoder_func(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_pipe_mbus_enable(intel_crtc);
> > @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
>
> Dont we need to make sure initial_watermarks is present or !NULL before calling it
> like we do in all other hooks?
We know it's non-NULL here. Eventually most (if not all) of the
other checks should disappear as well. But that requires finishing
the two stage watermarks for pre-g4x.
>
> Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
> either in this patch or another cleanup patch we should change it all to keep either crtc or
> intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc
>
> What do you think?
> But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
> in valleyview_crtc_enable(),
>
> Reviewed-by: Manasi navare <manasi.d.navare@intel.com>
>
> Manasi
>
> > intel_enable_pipe(pipe_config);
> >
> > intel_crtc_vblank_on(pipe_config);
> > @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state,
> > - pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> > else
> > intel_update_watermarks(intel_crtc);
> > intel_enable_pipe(pipe_config);
> > @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> > struct intel_crtc_state *old_crtc_state,
> > struct intel_crtc_state *new_crtc_state)
> > {
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > bool modeset = needs_modeset(new_crtc_state);
> >
> > @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> > }
> >
> > if (dev_priv->display.atomic_update_watermarks)
> > - dev_priv->display.atomic_update_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.atomic_update_watermarks(state, crtc);
> > }
> >
> > static void intel_update_crtc(struct intel_crtc *crtc,
> > @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> > if (!new_crtc_state->hw.active &&
> > !HAS_GMCH(dev_priv) &&
> > dev_priv->display.initial_watermarks)
> > - dev_priv->display.initial_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.initial_watermarks(state, crtc);
> > }
> >
> > static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> > @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > */
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (dev_priv->display.optimize_watermarks)
> > - dev_priv->display.optimize_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.optimize_watermarks(state, crtc);
> > }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> > /* Write calculated watermark values back */
> > for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> > crtc_state->wm.need_postvbl_update = true;
> > - dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> > + dev_priv->display.optimize_watermarks(intel_state, crtc);
> >
> > to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e0f67babe20..00fe4ed4fb96 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
> > int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> > int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> > void (*initial_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > void (*optimize_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > int (*compute_global_watermarks)(struct intel_atomic_state *state);
> > void (*update_wm)(struct intel_crtc *crtc);
> > int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 2d389e437e87..b180342f63a6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void g4x_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> > @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> > (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
> >
> > static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > const struct vlv_fifo_state *fifo_state =
> > &crtc_state->wm.vlv.fifo_state;
> > int sprite0_start, sprite1_start, fifo_size;
> > @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void vlv_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> > @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > }
> >
> > static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > enum pipe pipe = crtc->pipe;
> >
> > if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> > }
> >
> > static void skl_initial_wm(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > struct skl_ddb_values *results = &state->wm_results;
> >
> > if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> > mutex_lock(&dev_priv->wm.wm_mutex);
> >
> > if (crtc_state->uapi.active_changed)
> > - skl_atomic_update_crtc_wm(state, crtc_state);
> > + skl_atomic_update_crtc_wm(state, crtc);
> >
> > mutex_unlock(&dev_priv->wm.wm_mutex);
> > }
> > @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void ilk_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> > @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-15 15:18 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2019-11-15 15:18 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Nov 13, 2019 at 04:22:28PM -0800, Manasi Navare wrote:
> On Tue, Nov 12, 2019 at 04:14:59PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
> > time for the caller when it doesn't have to think what to pass.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
> > drivers/gpu/drm/i915/i915_drv.h | 6 +-
> > drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
> > 3 files changed, 53 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index ffadfd90c3cf..77b739cda053 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6177,9 +6177,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> > * we'll continue to update watermarks the old way, if flags tell
> > * us to.
> > */
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(intel_state,
> > - pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(intel_state, crtc);
> > else if (pipe_config->update_wm_pre)
> > intel_update_watermarks(crtc);
> > }
> > @@ -6527,8 +6526,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> > intel_enable_pipe(pipe_config);
> >
> > if (pipe_config->has_pch_encoder)
> > @@ -6671,8 +6670,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_ddi_enable_transcoder_func(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_pipe_mbus_enable(intel_crtc);
> > @@ -7062,7 +7061,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - dev_priv->display.initial_watermarks(state, pipe_config);
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
>
> Dont we need to make sure initial_watermarks is present or !NULL before calling it
> like we do in all other hooks?
We know it's non-NULL here. Eventually most (if not all) of the
other checks should disappear as well. But that requires finishing
the two stage watermarks for pre-g4x.
>
> Also some places we use intel_crtc vs crtc even though both are of type struct intel_crtc*,
> either in this patch or another cleanup patch we should change it all to keep either crtc or
> intel_crtc else there is a confusion between crtc being of type intel_crtc or drm_crtc
>
> What do you think?
> But that could be a separate change so after adding a check for if (dev_priv->display.initial_watermarks)
> in valleyview_crtc_enable(),
>
> Reviewed-by: Manasi navare <manasi.d.navare@intel.com>
>
> Manasi
>
> > intel_enable_pipe(pipe_config);
> >
> > intel_crtc_vblank_on(pipe_config);
> > @@ -7117,9 +7116,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > intel_disable_primary_plane(pipe_config);
> >
> > - if (dev_priv->display.initial_watermarks != NULL)
> > - dev_priv->display.initial_watermarks(state,
> > - pipe_config);
> > + if (dev_priv->display.initial_watermarks)
> > + dev_priv->display.initial_watermarks(state, intel_crtc);
> > else
> > intel_update_watermarks(intel_crtc);
> > intel_enable_pipe(pipe_config);
> > @@ -14291,6 +14289,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> > struct intel_crtc_state *old_crtc_state,
> > struct intel_crtc_state *new_crtc_state)
> > {
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > bool modeset = needs_modeset(new_crtc_state);
> >
> > @@ -14314,8 +14313,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> > }
> >
> > if (dev_priv->display.atomic_update_watermarks)
> > - dev_priv->display.atomic_update_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.atomic_update_watermarks(state, crtc);
> > }
> >
> > static void intel_update_crtc(struct intel_crtc *crtc,
> > @@ -14419,8 +14417,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> > if (!new_crtc_state->hw.active &&
> > !HAS_GMCH(dev_priv) &&
> > dev_priv->display.initial_watermarks)
> > - dev_priv->display.initial_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.initial_watermarks(state, crtc);
> > }
> >
> > static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> > @@ -14870,8 +14867,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > */
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (dev_priv->display.optimize_watermarks)
> > - dev_priv->display.optimize_watermarks(state,
> > - new_crtc_state);
> > + dev_priv->display.optimize_watermarks(state, crtc);
> > }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > @@ -16826,7 +16822,7 @@ static void sanitize_watermarks(struct drm_device *dev)
> > /* Write calculated watermark values back */
> > for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> > crtc_state->wm.need_postvbl_update = true;
> > - dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> > + dev_priv->display.optimize_watermarks(intel_state, crtc);
> >
> > to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e0f67babe20..00fe4ed4fb96 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
> > int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> > int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> > void (*initial_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > void (*optimize_watermarks)(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state);
> > + struct intel_crtc *crtc);
> > int (*compute_global_watermarks)(struct intel_atomic_state *state);
> > void (*update_wm)(struct intel_crtc *crtc);
> > int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 2d389e437e87..b180342f63a6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1520,10 +1520,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void g4x_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> > @@ -1532,10 +1533,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > @@ -1915,11 +1917,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> > (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
> >
> > static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > const struct vlv_fifo_state *fifo_state =
> > &crtc_state->wm.vlv.fifo_state;
> > int sprite0_start, sprite1_start, fifo_size;
> > @@ -2139,10 +2142,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void vlv_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> > @@ -2151,10 +2155,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > @@ -5491,11 +5496,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > }
> >
> > static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > enum pipe pipe = crtc->pipe;
> >
> > if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5505,10 +5511,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> > }
> >
> > static void skl_initial_wm(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > struct skl_ddb_values *results = &state->wm_results;
> >
> > if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
> > @@ -5517,7 +5524,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
> > mutex_lock(&dev_priv->wm.wm_mutex);
> >
> > if (crtc_state->uapi.active_changed)
> > - skl_atomic_update_crtc_wm(state, crtc_state);
> > + skl_atomic_update_crtc_wm(state, crtc);
> >
> > mutex_unlock(&dev_priv->wm.wm_mutex);
> > }
> > @@ -5573,10 +5580,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> > }
> >
> > static void ilk_initial_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > mutex_lock(&dev_priv->wm.wm_mutex);
> > crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> > @@ -5585,10 +5593,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> > }
> >
> > static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> > - struct intel_crtc_state *crtc_state)
> > + struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + const struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> >
> > if (!crtc_state->wm.need_postvbl_update)
> > return;
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the last 'dev' usage in ironlake_crtc_enable() by
passing dev_priv to cpt_verify_modeset().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 77b739cda053..6afdbfbb3264 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5462,9 +5462,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
-static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
+static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t dslreg = PIPEDSL(pipe);
u32 temp;
@@ -6538,7 +6538,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
- cpt_verify_modeset(dev, intel_crtc->pipe);
+ cpt_verify_modeset(dev_priv, pipe);
/*
* Must wait for vblank to avoid spurious PCH FIFO underruns.
--
2.23.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the last 'dev' usage in ironlake_crtc_enable() by
passing dev_priv to cpt_verify_modeset().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 77b739cda053..6afdbfbb3264 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5462,9 +5462,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
-static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
+static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t dslreg = PIPEDSL(pipe);
u32 temp;
@@ -6538,7 +6538,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
- cpt_verify_modeset(dev, intel_crtc->pipe);
+ cpt_verify_modeset(dev_priv, pipe);
/*
* Must wait for vblank to avoid spurious PCH FIFO underruns.
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-14 0:23 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:00PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the last 'dev' usage in ironlake_crtc_enable() by
> passing dev_priv to cpt_verify_modeset().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 77b739cda053..6afdbfbb3264 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5462,9 +5462,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
> lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> }
>
> -static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
> +static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> i915_reg_t dslreg = PIPEDSL(pipe);
> u32 temp;
>
> @@ -6538,7 +6538,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_encoders_enable(state, intel_crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> - cpt_verify_modeset(dev, intel_crtc->pipe);
> + cpt_verify_modeset(dev_priv, pipe);
>
> /*
> * Must wait for vblank to avoid spurious PCH FIFO underruns.
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-14 0:23 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:00PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the last 'dev' usage in ironlake_crtc_enable() by
> passing dev_priv to cpt_verify_modeset().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 77b739cda053..6afdbfbb3264 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5462,9 +5462,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
> lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
> }
>
> -static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
> +static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> i915_reg_t dslreg = PIPEDSL(pipe);
> u32 temp;
>
> @@ -6538,7 +6538,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_encoders_enable(state, intel_crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> - cpt_verify_modeset(dev, intel_crtc->pipe);
> + cpt_verify_modeset(dev_priv, pipe);
>
> /*
> * Must wait for vblank to avoid spurious PCH FIFO underruns.
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the horrible aliasing drm_crtc and intel_crtc variables
in the crtc enable/disable hooks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
1 file changed, 65 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6afdbfbb3264..b091b92a677c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6463,13 +6463,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
/*
@@ -6501,9 +6499,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
ironlake_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6527,7 +6525,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6535,7 +6533,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev_priv, pipe);
@@ -6596,22 +6594,21 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bool psl_clkgate_wa;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6641,7 +6638,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
@@ -6665,16 +6662,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
- icl_set_pipe_chicken(intel_crtc);
+ icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
if (INTEL_GEN(dev_priv) >= 11)
- icl_pipe_mbus_enable(intel_crtc);
+ icl_pipe_mbus_enable(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6688,7 +6685,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6722,11 +6719,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* Sometimes spurious CPU pipe underruns happen when the
@@ -6736,18 +6731,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(intel_crtc);
+ ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6770,7 +6765,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
I915_WRITE(PCH_DPLL_SEL, temp);
}
- ironlake_fdi_pll_disable(intel_crtc);
+ ironlake_fdi_pll_disable(crtc);
}
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6780,14 +6775,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6805,13 +6799,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(intel_crtc);
+ skylake_scaler_disable(crtc);
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7016,13 +7010,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
if (intel_crtc_has_dp_encoder(pipe_config))
@@ -7038,21 +7030,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(intel_crtc, pipe_config);
- chv_enable_pll(intel_crtc, pipe_config);
+ chv_prepare_pll(crtc, pipe_config);
+ chv_enable_pll(crtc, pipe_config);
} else {
- vlv_prepare_pll(intel_crtc, pipe_config);
- vlv_enable_pll(intel_crtc, pipe_config);
+ vlv_prepare_pll(crtc, pipe_config);
+ vlv_enable_pll(crtc, pipe_config);
}
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
i9xx_pfit_enable(pipe_config);
@@ -7061,12 +7053,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7081,13 +7073,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
i9xx_set_pll_dividers(pipe_config);
@@ -7100,14 +7090,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(intel_crtc, pipe_config);
+ i9xx_enable_pll(crtc, pipe_config);
i9xx_pfit_enable(pipe_config);
@@ -7117,14 +7107,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7145,11 +7135,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* On gen2 planes are double buffered but the pipe isn't, so we must
@@ -7158,15 +7146,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7177,13 +7165,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
--
2.23.0
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^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the horrible aliasing drm_crtc and intel_crtc variables
in the crtc enable/disable hooks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
1 file changed, 65 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6afdbfbb3264..b091b92a677c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6463,13 +6463,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
/*
@@ -6501,9 +6499,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
ironlake_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6527,7 +6525,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6535,7 +6533,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev_priv, pipe);
@@ -6596,22 +6594,21 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bool psl_clkgate_wa;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6641,7 +6638,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
@@ -6665,16 +6662,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
- icl_set_pipe_chicken(intel_crtc);
+ icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
if (INTEL_GEN(dev_priv) >= 11)
- icl_pipe_mbus_enable(intel_crtc);
+ icl_pipe_mbus_enable(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6688,7 +6685,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6722,11 +6719,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* Sometimes spurious CPU pipe underruns happen when the
@@ -6736,18 +6731,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(intel_crtc);
+ ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6770,7 +6765,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
I915_WRITE(PCH_DPLL_SEL, temp);
}
- ironlake_fdi_pll_disable(intel_crtc);
+ ironlake_fdi_pll_disable(crtc);
}
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6780,14 +6775,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6805,13 +6799,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(intel_crtc);
+ skylake_scaler_disable(crtc);
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7016,13 +7010,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
if (intel_crtc_has_dp_encoder(pipe_config))
@@ -7038,21 +7030,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(intel_crtc, pipe_config);
- chv_enable_pll(intel_crtc, pipe_config);
+ chv_prepare_pll(crtc, pipe_config);
+ chv_enable_pll(crtc, pipe_config);
} else {
- vlv_prepare_pll(intel_crtc, pipe_config);
- vlv_enable_pll(intel_crtc, pipe_config);
+ vlv_prepare_pll(crtc, pipe_config);
+ vlv_enable_pll(crtc, pipe_config);
}
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
i9xx_pfit_enable(pipe_config);
@@ -7061,12 +7053,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7081,13 +7073,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
i9xx_set_pll_dividers(pipe_config);
@@ -7100,14 +7090,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(intel_crtc, pipe_config);
+ i9xx_enable_pll(crtc, pipe_config);
i9xx_pfit_enable(pipe_config);
@@ -7117,14 +7107,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7145,11 +7135,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* On gen2 planes are double buffered but the pipe isn't, so we must
@@ -7158,15 +7146,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7177,13 +7165,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-14 0:27 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:27 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the horrible aliasing drm_crtc and intel_crtc variables
> in the crtc enable/disable hooks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Great this addresses my concern on intel_crtc vs crtc on the previous patch
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
> 1 file changed, 65 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6afdbfbb3264..b091b92a677c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6463,13 +6463,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> /*
> @@ -6501,9 +6499,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> ironlake_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> if (pipe_config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -6527,7 +6525,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> intel_enable_pipe(pipe_config);
>
> if (pipe_config->has_pch_encoder)
> @@ -6535,7 +6533,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev_priv, pipe);
> @@ -6596,22 +6594,21 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> bool psl_clkgate_wa;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(state, intel_crtc);
> + intel_encoders_pre_pll_enable(state, crtc);
>
> if (pipe_config->shared_dpll)
> intel_enable_shared_dpll(pipe_config);
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
> @@ -6641,7 +6638,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> @@ -6665,16 +6662,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_set_pipe_chicken(intel_crtc);
> + icl_set_pipe_chicken(crtc);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_enable_transcoder_func(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_pipe_mbus_enable(intel_crtc);
> + icl_pipe_mbus_enable(crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -6688,7 +6685,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
>
> if (psl_clkgate_wa) {
> intel_wait_for_vblank(dev_priv, pipe);
> @@ -6722,11 +6719,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> /*
> * Sometimes spurious CPU pipe underruns happen when the
> @@ -6736,18 +6731,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> ironlake_pfit_disable(old_crtc_state);
>
> if (old_crtc_state->has_pch_encoder)
> - ironlake_fdi_disable(intel_crtc);
> + ironlake_fdi_disable(crtc);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> if (old_crtc_state->has_pch_encoder) {
> ironlake_disable_pch_transcoder(dev_priv, pipe);
> @@ -6770,7 +6765,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> I915_WRITE(PCH_DPLL_SEL, temp);
> }
>
> - ironlake_fdi_pll_disable(intel_crtc);
> + ironlake_fdi_pll_disable(crtc);
> }
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> @@ -6780,14 +6775,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -6805,13 +6799,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_dsc_disable(old_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_scaler_disable(intel_crtc);
> + skylake_scaler_disable(crtc);
> else
> ironlake_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> - intel_encoders_post_pll_disable(state, intel_crtc);
> + intel_encoders_post_pll_disable(state, crtc);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -7016,13 +7010,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> @@ -7038,21 +7030,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> i9xx_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_pll_enable(state, intel_crtc);
> + intel_encoders_pre_pll_enable(state, crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> - chv_prepare_pll(intel_crtc, pipe_config);
> - chv_enable_pll(intel_crtc, pipe_config);
> + chv_prepare_pll(crtc, pipe_config);
> + chv_enable_pll(crtc, pipe_config);
> } else {
> - vlv_prepare_pll(intel_crtc, pipe_config);
> - vlv_enable_pll(intel_crtc, pipe_config);
> + vlv_prepare_pll(crtc, pipe_config);
> + vlv_enable_pll(crtc, pipe_config);
> }
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7061,12 +7053,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
> }
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> @@ -7081,13 +7073,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> i9xx_set_pll_dividers(pipe_config);
> @@ -7100,14 +7090,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> i9xx_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> - i9xx_enable_pll(intel_crtc, pipe_config);
> + i9xx_enable_pll(crtc, pipe_config);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7117,14 +7107,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> else
> - intel_update_watermarks(intel_crtc);
> + intel_update_watermarks(crtc);
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
> }
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -7145,11 +7135,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> /*
> * On gen2 planes are double buffered but the pipe isn't, so we must
> @@ -7158,15 +7146,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (IS_GEN(dev_priv, 2))
> intel_wait_for_vblank(dev_priv, pipe);
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> i9xx_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev_priv))
> @@ -7177,13 +7165,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> i9xx_disable_pll(old_crtc_state);
> }
>
> - intel_encoders_post_pll_disable(state, intel_crtc);
> + intel_encoders_post_pll_disable(state, crtc);
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> if (!dev_priv->display.initial_watermarks)
> - intel_update_watermarks(intel_crtc);
> + intel_update_watermarks(crtc);
>
> /* clock the pipe down to 640x480@60 to potentially save power */
> if (IS_I830(dev_priv))
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-14 0:27 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:27 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the horrible aliasing drm_crtc and intel_crtc variables
> in the crtc enable/disable hooks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Great this addresses my concern on intel_crtc vs crtc on the previous patch
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
> 1 file changed, 65 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6afdbfbb3264..b091b92a677c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6463,13 +6463,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> /*
> @@ -6501,9 +6499,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> ironlake_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> if (pipe_config->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -6527,7 +6525,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> intel_enable_pipe(pipe_config);
>
> if (pipe_config->has_pch_encoder)
> @@ -6535,7 +6533,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
>
> if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev_priv, pipe);
> @@ -6596,22 +6594,21 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> bool psl_clkgate_wa;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> - intel_encoders_pre_pll_enable(state, intel_crtc);
> + intel_encoders_pre_pll_enable(state, crtc);
>
> if (pipe_config->shared_dpll)
> intel_enable_shared_dpll(pipe_config);
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
> @@ -6641,7 +6638,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> @@ -6665,16 +6662,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_set_pipe_chicken(intel_crtc);
> + icl_set_pipe_chicken(crtc);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_enable_transcoder_func(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_pipe_mbus_enable(intel_crtc);
> + icl_pipe_mbus_enable(crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -6688,7 +6685,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
>
> if (psl_clkgate_wa) {
> intel_wait_for_vblank(dev_priv, pipe);
> @@ -6722,11 +6719,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> /*
> * Sometimes spurious CPU pipe underruns happen when the
> @@ -6736,18 +6731,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> ironlake_pfit_disable(old_crtc_state);
>
> if (old_crtc_state->has_pch_encoder)
> - ironlake_fdi_disable(intel_crtc);
> + ironlake_fdi_disable(crtc);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> if (old_crtc_state->has_pch_encoder) {
> ironlake_disable_pch_transcoder(dev_priv, pipe);
> @@ -6770,7 +6765,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> I915_WRITE(PCH_DPLL_SEL, temp);
> }
>
> - ironlake_fdi_pll_disable(intel_crtc);
> + ironlake_fdi_pll_disable(crtc);
> }
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> @@ -6780,14 +6775,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> @@ -6805,13 +6799,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_dsc_disable(old_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_scaler_disable(intel_crtc);
> + skylake_scaler_disable(crtc);
> else
> ironlake_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> - intel_encoders_post_pll_disable(state, intel_crtc);
> + intel_encoders_post_pll_disable(state, crtc);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -7016,13 +7010,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> if (intel_crtc_has_dp_encoder(pipe_config))
> @@ -7038,21 +7030,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> i9xx_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_pll_enable(state, intel_crtc);
> + intel_encoders_pre_pll_enable(state, crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> - chv_prepare_pll(intel_crtc, pipe_config);
> - chv_enable_pll(intel_crtc, pipe_config);
> + chv_prepare_pll(crtc, pipe_config);
> + chv_enable_pll(crtc, pipe_config);
> } else {
> - vlv_prepare_pll(intel_crtc, pipe_config);
> - vlv_enable_pll(intel_crtc, pipe_config);
> + vlv_prepare_pll(crtc, pipe_config);
> + vlv_enable_pll(crtc, pipe_config);
> }
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7061,12 +7053,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(pipe_config);
>
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
> }
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> @@ -7081,13 +7073,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> - if (WARN_ON(intel_crtc->active))
> + if (WARN_ON(crtc->active))
> return;
>
> i9xx_set_pll_dividers(pipe_config);
> @@ -7100,14 +7090,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> i9xx_set_pipeconf(pipe_config);
>
> - intel_crtc->active = true;
> + crtc->active = true;
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> - intel_encoders_pre_enable(state, intel_crtc);
> + intel_encoders_pre_enable(state, crtc);
>
> - i9xx_enable_pll(intel_crtc, pipe_config);
> + i9xx_enable_pll(crtc, pipe_config);
>
> i9xx_pfit_enable(pipe_config);
>
> @@ -7117,14 +7107,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, intel_crtc);
> + dev_priv->display.initial_watermarks(state, crtc);
> else
> - intel_update_watermarks(intel_crtc);
> + intel_update_watermarks(crtc);
> intel_enable_pipe(pipe_config);
>
> intel_crtc_vblank_on(pipe_config);
>
> - intel_encoders_enable(state, intel_crtc);
> + intel_encoders_enable(state, crtc);
> }
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -7145,11 +7135,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> /*
> * On gen2 planes are double buffered but the pipe isn't, so we must
> @@ -7158,15 +7146,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (IS_GEN(dev_priv, 2))
> intel_wait_for_vblank(dev_priv, pipe);
>
> - intel_encoders_disable(state, intel_crtc);
> + intel_encoders_disable(state, crtc);
>
> - intel_crtc_vblank_off(intel_crtc);
> + intel_crtc_vblank_off(crtc);
>
> intel_disable_pipe(old_crtc_state);
>
> i9xx_pfit_disable(old_crtc_state);
>
> - intel_encoders_post_disable(state, intel_crtc);
> + intel_encoders_post_disable(state, crtc);
>
> if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev_priv))
> @@ -7177,13 +7165,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> i9xx_disable_pll(old_crtc_state);
> }
>
> - intel_encoders_post_pll_disable(state, intel_crtc);
> + intel_encoders_post_pll_disable(state, crtc);
>
> if (!IS_GEN(dev_priv, 2))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> if (!dev_priv->display.initial_watermarks)
> - intel_update_watermarks(intel_crtc);
> + intel_update_watermarks(crtc);
>
> /* clock the pipe down to 640x480@60 to potentially save power */
> if (IS_I830(dev_priv))
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
The 'pipe_config' name is a zombie that we need to finally put down.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
1 file changed, 86 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b091b92a677c..11953fe06488 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
+static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (pipe_config->has_pch_encoder)
- intel_prepare_shared_dpll(pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ intel_prepare_shared_dpll(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- ironlake_set_pipeconf(pipe_config);
+ ironlake_set_pipeconf(new_crtc_state);
crtc->active = true;
intel_encoders_pre_enable(state, crtc);
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(pipe_config);
+ ironlake_fdi_pll_enable(new_crtc_state);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
}
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- ironlake_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ ironlake_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
* some interlaced HDMI modes. Let's do the double wait always
* in case there are more corner cases we don't know about.
*/
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
+static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
bool psl_clkgate_wa;
if (WARN_ON(crtc->active))
@@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
- if (pipe_config->shared_dpll)
- intel_enable_shared_dpll(pipe_config);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
- icl_enable_trans_port_sync(pipe_config);
+ icl_enable_trans_port_sync(new_crtc_state);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_src_size(new_crtc_state);
if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder)) {
+ !transcoder_is_dsi(cpu_transcoder))
I915_WRITE(PIPE_MULT(cpu_transcoder),
- pipe_config->pixel_multiplier - 1);
- }
+ new_crtc_state->pixel_multiplier - 1);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
if (!transcoder_is_dsi(cpu_transcoder))
- haswell_set_pipeconf(pipe_config);
+ haswell_set_pipeconf(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(pipe_config);
+ bdw_set_pipemisc(new_crtc_state);
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- pipe_config->pch_pfit.enabled;
+ new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_pfit_enable(pipe_config);
+ skylake_pfit_enable(new_crtc_state);
else
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
if (INTEL_GEN(dev_priv) < 9)
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_ddi_enable_transcoder_func(pipe_config);
+ intel_ddi_enable_transcoder_func(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
@@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- lpt_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ lpt_pch_enable(state, new_crtc_state);
- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(pipe_config, true);
+ if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
+ intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
- hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
+ hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
@@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
+static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
I915_WRITE(CHV_CANVAS(pipe), 0);
}
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(crtc, pipe_config);
- chv_enable_pll(crtc, pipe_config);
+ chv_prepare_pll(crtc, new_crtc_state);
+ chv_enable_pll(crtc, new_crtc_state);
} else {
- vlv_prepare_pll(crtc, pipe_config);
- vlv_enable_pll(crtc, pipe_config);
+ vlv_prepare_pll(crtc, new_crtc_state);
+ vlv_enable_pll(crtc, new_crtc_state);
}
intel_encoders_pre_enable(state, crtc);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
@@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
+static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- i9xx_set_pll_dividers(pipe_config);
+ i9xx_set_pll_dividers(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(crtc, pipe_config);
+ i9xx_enable_pll(crtc, new_crtc_state);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
--
2.23.0
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^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
The 'pipe_config' name is a zombie that we need to finally put down.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
1 file changed, 86 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b091b92a677c..11953fe06488 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
+static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (pipe_config->has_pch_encoder)
- intel_prepare_shared_dpll(pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ intel_prepare_shared_dpll(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- ironlake_set_pipeconf(pipe_config);
+ ironlake_set_pipeconf(new_crtc_state);
crtc->active = true;
intel_encoders_pre_enable(state, crtc);
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(pipe_config);
+ ironlake_fdi_pll_enable(new_crtc_state);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
}
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- ironlake_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ ironlake_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
* some interlaced HDMI modes. Let's do the double wait always
* in case there are more corner cases we don't know about.
*/
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
+static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
bool psl_clkgate_wa;
if (WARN_ON(crtc->active))
@@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
- if (pipe_config->shared_dpll)
- intel_enable_shared_dpll(pipe_config);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
- icl_enable_trans_port_sync(pipe_config);
+ icl_enable_trans_port_sync(new_crtc_state);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_src_size(new_crtc_state);
if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder)) {
+ !transcoder_is_dsi(cpu_transcoder))
I915_WRITE(PIPE_MULT(cpu_transcoder),
- pipe_config->pixel_multiplier - 1);
- }
+ new_crtc_state->pixel_multiplier - 1);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
if (!transcoder_is_dsi(cpu_transcoder))
- haswell_set_pipeconf(pipe_config);
+ haswell_set_pipeconf(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(pipe_config);
+ bdw_set_pipemisc(new_crtc_state);
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- pipe_config->pch_pfit.enabled;
+ new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_pfit_enable(pipe_config);
+ skylake_pfit_enable(new_crtc_state);
else
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
if (INTEL_GEN(dev_priv) < 9)
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_ddi_enable_transcoder_func(pipe_config);
+ intel_ddi_enable_transcoder_func(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
@@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- lpt_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ lpt_pch_enable(state, new_crtc_state);
- if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
- intel_ddi_set_vc_payload_alloc(pipe_config, true);
+ if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
+ intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
- hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
+ hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
@@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
+static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
I915_WRITE(CHV_CANVAS(pipe), 0);
}
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(crtc, pipe_config);
- chv_enable_pll(crtc, pipe_config);
+ chv_prepare_pll(crtc, new_crtc_state);
+ chv_enable_pll(crtc, new_crtc_state);
} else {
- vlv_prepare_pll(crtc, pipe_config);
- vlv_enable_pll(crtc, pipe_config);
+ vlv_prepare_pll(crtc, new_crtc_state);
+ vlv_enable_pll(crtc, new_crtc_state);
}
intel_encoders_pre_enable(state, crtc);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
@@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
+static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- i9xx_set_pll_dividers(pipe_config);
+ i9xx_set_pll_dividers(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(crtc, pipe_config);
+ i9xx_enable_pll(crtc, new_crtc_state);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-14 0:35 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
> The 'pipe_config' name is a zombie that we need to finally put down.
So basically use pipe_config only in atomic check functions
like compute_config() etc and then all atomic commit hooks replace that
with new_crtc_state ?
Replacements below look good,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
> 1 file changed, 86 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b091b92a677c..11953fe06488 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> plane->disable_plane(plane, crtc_state);
> }
>
> -static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - if (pipe_config->has_pch_encoder)
> - intel_prepare_shared_dpll(pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + intel_prepare_shared_dpll(new_crtc_state);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder) {
> - intel_cpu_transcoder_set_m_n(pipe_config,
> - &pipe_config->fdi_m_n, NULL);
> - }
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> - ironlake_set_pipeconf(pipe_config);
> + ironlake_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> intel_encoders_pre_enable(state, crtc);
>
> - if (pipe_config->has_pch_encoder) {
> + if (new_crtc_state->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> * cpu pipes, hence this is separate from all the other fdi/pch
> * enabling. */
> - ironlake_fdi_pll_enable(pipe_config);
> + ironlake_fdi_pll_enable(new_crtc_state);
> } else {
> assert_fdi_tx_disabled(dev_priv, pipe);
> assert_fdi_rx_disabled(dev_priv, pipe);
> }
>
> - ironlake_pfit_enable(pipe_config);
> + ironlake_pfit_enable(new_crtc_state);
>
> /*
> * On ILK+ LUT must be loaded before the pipe is running but with
> * clocks enabled
> */
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder)
> - ironlake_pch_enable(state, pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + ironlake_pch_enable(state, new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
>
> @@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> * some interlaced HDMI modes. Let's do the double wait always
> * in case there are more corner cases we don't know about.
> */
> - if (pipe_config->has_pch_encoder) {
> + if (new_crtc_state->has_pch_encoder) {
> intel_wait_for_vblank(dev_priv, pipe);
> intel_wait_for_vblank(dev_priv, pipe);
> }
> @@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
>
> -static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> bool psl_clkgate_wa;
>
> if (WARN_ON(crtc->active))
> @@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_pll_enable(state, crtc);
>
> - if (pipe_config->shared_dpll)
> - intel_enable_shared_dpll(pipe_config);
> + if (new_crtc_state->shared_dpll)
> + intel_enable_shared_dpll(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_pipe_timings(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_enable_trans_port_sync(pipe_config);
> + icl_enable_trans_port_sync(new_crtc_state);
>
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_src_size(new_crtc_state);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(cpu_transcoder)) {
> + !transcoder_is_dsi(cpu_transcoder))
> I915_WRITE(PIPE_MULT(cpu_transcoder),
> - pipe_config->pixel_multiplier - 1);
> - }
> + new_crtc_state->pixel_multiplier - 1);
>
> - if (pipe_config->has_pch_encoder) {
> - intel_cpu_transcoder_set_m_n(pipe_config,
> - &pipe_config->fdi_m_n, NULL);
> - }
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - haswell_set_pipeconf(pipe_config);
> + haswell_set_pipeconf(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> - bdw_set_pipemisc(pipe_config);
> + bdw_set_pipemisc(new_crtc_state);
>
> crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> - pipe_config->pch_pfit.enabled;
> + new_crtc_state->pch_pfit.enabled;
> if (psl_clkgate_wa)
> glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_pfit_enable(pipe_config);
> + skylake_pfit_enable(new_crtc_state);
> else
> - ironlake_pfit_enable(pipe_config);
> + ironlake_pfit_enable(new_crtc_state);
>
> /*
> * On ILK+ LUT must be loaded before the pipe is running but with
> * clocks enabled
> */
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> if (INTEL_GEN(dev_priv) < 9)
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 11)
> icl_set_pipe_chicken(crtc);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_ddi_enable_transcoder_func(pipe_config);
> + intel_ddi_enable_transcoder_func(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> @@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder)
> - lpt_pch_enable(state, pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + lpt_pch_enable(state, new_crtc_state);
>
> - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> + if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
> + intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
>
> @@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> /* If we change the relative order between pipe/planes enabling, we need
> * to change the workaround. */
> - hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
> if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> @@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> intel_display_power_put_unchecked(dev_priv, domain);
> }
>
> -static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(crtc->active))
> return;
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> I915_WRITE(CHV_CANVAS(pipe), 0);
> }
>
> - i9xx_set_pipeconf(pipe_config);
> + i9xx_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_encoders_pre_pll_enable(state, crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> - chv_prepare_pll(crtc, pipe_config);
> - chv_enable_pll(crtc, pipe_config);
> + chv_prepare_pll(crtc, new_crtc_state);
> + chv_enable_pll(crtc, new_crtc_state);
> } else {
> - vlv_prepare_pll(crtc, pipe_config);
> - vlv_enable_pll(crtc, pipe_config);
> + vlv_prepare_pll(crtc, new_crtc_state);
> + vlv_enable_pll(crtc, new_crtc_state);
> }
>
> intel_encoders_pre_enable(state, crtc);
>
> - i9xx_pfit_enable(pipe_config);
> + i9xx_pfit_enable(new_crtc_state);
>
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> dev_priv->display.initial_watermarks(state, crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
> }
> @@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> }
>
> -static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(crtc->active))
> return;
>
> - i9xx_set_pll_dividers(pipe_config);
> + i9xx_set_pll_dividers(new_crtc_state);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> - i9xx_set_pipeconf(pipe_config);
> + i9xx_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_enable(state, crtc);
>
> - i9xx_enable_pll(crtc, pipe_config);
> + i9xx_enable_pll(crtc, new_crtc_state);
>
> - i9xx_pfit_enable(pipe_config);
> + i9xx_pfit_enable(new_crtc_state);
>
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> else
> intel_update_watermarks(crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
> }
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-14 0:35 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
> The 'pipe_config' name is a zombie that we need to finally put down.
So basically use pipe_config only in atomic check functions
like compute_config() etc and then all atomic commit hooks replace that
with new_crtc_state ?
Replacements below look good,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
> 1 file changed, 86 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b091b92a677c..11953fe06488 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> plane->disable_plane(plane, crtc_state);
> }
>
> -static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - if (pipe_config->has_pch_encoder)
> - intel_prepare_shared_dpll(pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + intel_prepare_shared_dpll(new_crtc_state);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder) {
> - intel_cpu_transcoder_set_m_n(pipe_config,
> - &pipe_config->fdi_m_n, NULL);
> - }
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> - ironlake_set_pipeconf(pipe_config);
> + ironlake_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> intel_encoders_pre_enable(state, crtc);
>
> - if (pipe_config->has_pch_encoder) {
> + if (new_crtc_state->has_pch_encoder) {
> /* Note: FDI PLL enabling _must_ be done before we enable the
> * cpu pipes, hence this is separate from all the other fdi/pch
> * enabling. */
> - ironlake_fdi_pll_enable(pipe_config);
> + ironlake_fdi_pll_enable(new_crtc_state);
> } else {
> assert_fdi_tx_disabled(dev_priv, pipe);
> assert_fdi_rx_disabled(dev_priv, pipe);
> }
>
> - ironlake_pfit_enable(pipe_config);
> + ironlake_pfit_enable(new_crtc_state);
>
> /*
> * On ILK+ LUT must be loaded before the pipe is running but with
> * clocks enabled
> */
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder)
> - ironlake_pch_enable(state, pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + ironlake_pch_enable(state, new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
>
> @@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> * some interlaced HDMI modes. Let's do the double wait always
> * in case there are more corner cases we don't know about.
> */
> - if (pipe_config->has_pch_encoder) {
> + if (new_crtc_state->has_pch_encoder) {
> intel_wait_for_vblank(dev_priv, pipe);
> intel_wait_for_vblank(dev_priv, pipe);
> }
> @@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
>
> -static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> bool psl_clkgate_wa;
>
> if (WARN_ON(crtc->active))
> @@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_pll_enable(state, crtc);
>
> - if (pipe_config->shared_dpll)
> - intel_enable_shared_dpll(pipe_config);
> + if (new_crtc_state->shared_dpll)
> + intel_enable_shared_dpll(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_pipe_timings(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icl_enable_trans_port_sync(pipe_config);
> + icl_enable_trans_port_sync(new_crtc_state);
>
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_src_size(new_crtc_state);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(cpu_transcoder)) {
> + !transcoder_is_dsi(cpu_transcoder))
> I915_WRITE(PIPE_MULT(cpu_transcoder),
> - pipe_config->pixel_multiplier - 1);
> - }
> + new_crtc_state->pixel_multiplier - 1);
>
> - if (pipe_config->has_pch_encoder) {
> - intel_cpu_transcoder_set_m_n(pipe_config,
> - &pipe_config->fdi_m_n, NULL);
> - }
> + if (new_crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(new_crtc_state,
> + &new_crtc_state->fdi_m_n, NULL);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - haswell_set_pipeconf(pipe_config);
> + haswell_set_pipeconf(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> - bdw_set_pipemisc(pipe_config);
> + bdw_set_pipemisc(new_crtc_state);
>
> crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> - pipe_config->pch_pfit.enabled;
> + new_crtc_state->pch_pfit.enabled;
> if (psl_clkgate_wa)
> glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_pfit_enable(pipe_config);
> + skylake_pfit_enable(new_crtc_state);
> else
> - ironlake_pfit_enable(pipe_config);
> + ironlake_pfit_enable(new_crtc_state);
>
> /*
> * On ILK+ LUT must be loaded before the pipe is running but with
> * clocks enabled
> */
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> if (INTEL_GEN(dev_priv) < 9)
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 11)
> icl_set_pipe_chicken(crtc);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_ddi_enable_transcoder_func(pipe_config);
> + intel_ddi_enable_transcoder_func(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> @@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - if (pipe_config->has_pch_encoder)
> - lpt_pch_enable(state, pipe_config);
> + if (new_crtc_state->has_pch_encoder)
> + lpt_pch_enable(state, new_crtc_state);
>
> - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> + if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
> + intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
>
> @@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> /* If we change the relative order between pipe/planes enabling, we need
> * to change the workaround. */
> - hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
> if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> @@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> intel_display_power_put_unchecked(dev_priv, domain);
> }
>
> -static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(crtc->active))
> return;
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> I915_WRITE(CHV_CANVAS(pipe), 0);
> }
>
> - i9xx_set_pipeconf(pipe_config);
> + i9xx_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_encoders_pre_pll_enable(state, crtc);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> - chv_prepare_pll(crtc, pipe_config);
> - chv_enable_pll(crtc, pipe_config);
> + chv_prepare_pll(crtc, new_crtc_state);
> + chv_enable_pll(crtc, new_crtc_state);
> } else {
> - vlv_prepare_pll(crtc, pipe_config);
> - vlv_enable_pll(crtc, pipe_config);
> + vlv_prepare_pll(crtc, new_crtc_state);
> + vlv_enable_pll(crtc, new_crtc_state);
> }
>
> intel_encoders_pre_enable(state, crtc);
>
> - i9xx_pfit_enable(pipe_config);
> + i9xx_pfit_enable(new_crtc_state);
>
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> dev_priv->display.initial_watermarks(state, crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
> }
> @@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> }
>
> -static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> +static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(crtc->active))
> return;
>
> - i9xx_set_pll_dividers(pipe_config);
> + i9xx_set_pll_dividers(new_crtc_state);
>
> - if (intel_crtc_has_dp_encoder(pipe_config))
> - intel_dp_set_m_n(pipe_config, M1_N1);
> + if (intel_crtc_has_dp_encoder(new_crtc_state))
> + intel_dp_set_m_n(new_crtc_state, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> - intel_set_pipe_src_size(pipe_config);
> + intel_set_pipe_timings(new_crtc_state);
> + intel_set_pipe_src_size(new_crtc_state);
>
> - i9xx_set_pipeconf(pipe_config);
> + i9xx_set_pipeconf(new_crtc_state);
>
> crtc->active = true;
>
> @@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_enable(state, crtc);
>
> - i9xx_enable_pll(crtc, pipe_config);
> + i9xx_enable_pll(crtc, new_crtc_state);
>
> - i9xx_pfit_enable(pipe_config);
> + i9xx_pfit_enable(new_crtc_state);
>
> - intel_color_load_luts(pipe_config);
> - intel_color_commit(pipe_config);
> + intel_color_load_luts(new_crtc_state);
> + intel_color_commit(new_crtc_state);
> /* update DSPCNTR to configure gamma for pipe bottom color */
> - intel_disable_primary_plane(pipe_config);
> + intel_disable_primary_plane(new_crtc_state);
>
> if (dev_priv->display.initial_watermarks)
> dev_priv->display.initial_watermarks(state, crtc);
> else
> intel_update_watermarks(crtc);
> - intel_enable_pipe(pipe_config);
> + intel_enable_pipe(new_crtc_state);
>
> - intel_crtc_vblank_on(pipe_config);
> + intel_crtc_vblank_on(new_crtc_state);
>
> intel_encoders_enable(state, crtc);
> }
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-15 15:15 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2019-11-15 15:15 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Nov 13, 2019 at 04:35:47PM -0800, Manasi Navare wrote:
> On Tue, Nov 12, 2019 at 04:15:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
> > The 'pipe_config' name is a zombie that we need to finally put down.
>
> So basically use pipe_config only in atomic check functions
> like compute_config() etc and then all atomic commit hooks replace that
> with new_crtc_state ?
No. 'pipe_config' should be disappeared entirely.
>
> Replacements below look good,
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
> > 1 file changed, 86 insertions(+), 89 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index b091b92a677c..11953fe06488 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> > plane->disable_plane(plane, crtc_state);
> > }
> >
> > -static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > @@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> > intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> >
> > - if (pipe_config->has_pch_encoder)
> > - intel_prepare_shared_dpll(pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_prepare_shared_dpll(new_crtc_state);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder) {
> > - intel_cpu_transcoder_set_m_n(pipe_config,
> > - &pipe_config->fdi_m_n, NULL);
> > - }
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > + &new_crtc_state->fdi_m_n, NULL);
> >
> > - ironlake_set_pipeconf(pipe_config);
> > + ironlake_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - if (pipe_config->has_pch_encoder) {
> > + if (new_crtc_state->has_pch_encoder) {
> > /* Note: FDI PLL enabling _must_ be done before we enable the
> > * cpu pipes, hence this is separate from all the other fdi/pch
> > * enabling. */
> > - ironlake_fdi_pll_enable(pipe_config);
> > + ironlake_fdi_pll_enable(new_crtc_state);
> > } else {
> > assert_fdi_tx_disabled(dev_priv, pipe);
> > assert_fdi_rx_disabled(dev_priv, pipe);
> > }
> >
> > - ironlake_pfit_enable(pipe_config);
> > + ironlake_pfit_enable(new_crtc_state);
> >
> > /*
> > * On ILK+ LUT must be loaded before the pipe is running but with
> > * clocks enabled
> > */
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder)
> > - ironlake_pch_enable(state, pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + ironlake_pch_enable(state, new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> >
> > @@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > * some interlaced HDMI modes. Let's do the double wait always
> > * in case there are more corner cases we don't know about.
> > */
> > - if (pipe_config->has_pch_encoder) {
> > + if (new_crtc_state->has_pch_encoder) {
> > intel_wait_for_vblank(dev_priv, pipe);
> > intel_wait_for_vblank(dev_priv, pipe);
> > }
> > @@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> > }
> >
> > -static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> > - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> > bool psl_clkgate_wa;
> >
> > if (WARN_ON(crtc->active))
> > @@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > - if (pipe_config->shared_dpll)
> > - intel_enable_shared_dpll(pipe_config);
> > + if (new_crtc_state->shared_dpll)
> > + intel_enable_shared_dpll(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_set_pipe_timings(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > - icl_enable_trans_port_sync(pipe_config);
> > + icl_enable_trans_port_sync(new_crtc_state);
> >
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > if (cpu_transcoder != TRANSCODER_EDP &&
> > - !transcoder_is_dsi(cpu_transcoder)) {
> > + !transcoder_is_dsi(cpu_transcoder))
> > I915_WRITE(PIPE_MULT(cpu_transcoder),
> > - pipe_config->pixel_multiplier - 1);
> > - }
> > + new_crtc_state->pixel_multiplier - 1);
> >
> > - if (pipe_config->has_pch_encoder) {
> > - intel_cpu_transcoder_set_m_n(pipe_config,
> > - &pipe_config->fdi_m_n, NULL);
> > - }
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > + &new_crtc_state->fdi_m_n, NULL);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - haswell_set_pipeconf(pipe_config);
> > + haswell_set_pipeconf(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > - bdw_set_pipemisc(pipe_config);
> > + bdw_set_pipemisc(new_crtc_state);
> >
> > crtc->active = true;
> >
> > /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> > psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > - pipe_config->pch_pfit.enabled;
> > + new_crtc_state->pch_pfit.enabled;
> > if (psl_clkgate_wa)
> > glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
> >
> > if (INTEL_GEN(dev_priv) >= 9)
> > - skylake_pfit_enable(pipe_config);
> > + skylake_pfit_enable(new_crtc_state);
> > else
> > - ironlake_pfit_enable(pipe_config);
> > + ironlake_pfit_enable(new_crtc_state);
> >
> > /*
> > * On ILK+ LUT must be loaded before the pipe is running but with
> > * clocks enabled
> > */
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> > if (INTEL_GEN(dev_priv) < 9)
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_set_pipe_chicken(crtc);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_ddi_enable_transcoder_func(pipe_config);
> > + intel_ddi_enable_transcoder_func(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > @@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder)
> > - lpt_pch_enable(state, pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + lpt_pch_enable(state, new_crtc_state);
> >
> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> > + if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
> > + intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> >
> > @@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > /* If we change the relative order between pipe/planes enabling, we need
> > * to change the workaround. */
> > - hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> > + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
> > if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > @@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> > intel_display_power_put_unchecked(dev_priv, domain);
> > }
> >
> > -static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > if (WARN_ON(crtc->active))
> > return;
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> > I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> > I915_WRITE(CHV_CANVAS(pipe), 0);
> > }
> >
> > - i9xx_set_pipeconf(pipe_config);
> > + i9xx_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > @@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > if (IS_CHERRYVIEW(dev_priv)) {
> > - chv_prepare_pll(crtc, pipe_config);
> > - chv_enable_pll(crtc, pipe_config);
> > + chv_prepare_pll(crtc, new_crtc_state);
> > + chv_enable_pll(crtc, new_crtc_state);
> > } else {
> > - vlv_prepare_pll(crtc, pipe_config);
> > - vlv_enable_pll(crtc, pipe_config);
> > + vlv_prepare_pll(crtc, new_crtc_state);
> > + vlv_enable_pll(crtc, new_crtc_state);
> > }
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - i9xx_pfit_enable(pipe_config);
> > + i9xx_pfit_enable(new_crtc_state);
> >
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > dev_priv->display.initial_watermarks(state, crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> > }
> > @@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> > I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> > }
> >
> > -static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > if (WARN_ON(crtc->active))
> > return;
> >
> > - i9xx_set_pll_dividers(pipe_config);
> > + i9xx_set_pll_dividers(new_crtc_state);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > - i9xx_set_pipeconf(pipe_config);
> > + i9xx_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > @@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - i9xx_enable_pll(crtc, pipe_config);
> > + i9xx_enable_pll(crtc, new_crtc_state);
> >
> > - i9xx_pfit_enable(pipe_config);
> > + i9xx_pfit_enable(new_crtc_state);
> >
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > else
> > intel_update_watermarks(crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> > }
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-15 15:15 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2019-11-15 15:15 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Nov 13, 2019 at 04:35:47PM -0800, Manasi Navare wrote:
> On Tue, Nov 12, 2019 at 04:15:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
> > The 'pipe_config' name is a zombie that we need to finally put down.
>
> So basically use pipe_config only in atomic check functions
> like compute_config() etc and then all atomic commit hooks replace that
> with new_crtc_state ?
No. 'pipe_config' should be disappeared entirely.
>
> Replacements below look good,
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 175 +++++++++----------
> > 1 file changed, 86 insertions(+), 89 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index b091b92a677c..11953fe06488 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6460,10 +6460,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> > plane->disable_plane(plane, crtc_state);
> > }
> >
> > -static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > @@ -6483,55 +6483,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> > intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> >
> > - if (pipe_config->has_pch_encoder)
> > - intel_prepare_shared_dpll(pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_prepare_shared_dpll(new_crtc_state);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder) {
> > - intel_cpu_transcoder_set_m_n(pipe_config,
> > - &pipe_config->fdi_m_n, NULL);
> > - }
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > + &new_crtc_state->fdi_m_n, NULL);
> >
> > - ironlake_set_pipeconf(pipe_config);
> > + ironlake_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - if (pipe_config->has_pch_encoder) {
> > + if (new_crtc_state->has_pch_encoder) {
> > /* Note: FDI PLL enabling _must_ be done before we enable the
> > * cpu pipes, hence this is separate from all the other fdi/pch
> > * enabling. */
> > - ironlake_fdi_pll_enable(pipe_config);
> > + ironlake_fdi_pll_enable(new_crtc_state);
> > } else {
> > assert_fdi_tx_disabled(dev_priv, pipe);
> > assert_fdi_rx_disabled(dev_priv, pipe);
> > }
> >
> > - ironlake_pfit_enable(pipe_config);
> > + ironlake_pfit_enable(new_crtc_state);
> >
> > /*
> > * On ILK+ LUT must be loaded before the pipe is running but with
> > * clocks enabled
> > */
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder)
> > - ironlake_pch_enable(state, pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + ironlake_pch_enable(state, new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> >
> > @@ -6544,7 +6543,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> > * some interlaced HDMI modes. Let's do the double wait always
> > * in case there are more corner cases we don't know about.
> > */
> > - if (pipe_config->has_pch_encoder) {
> > + if (new_crtc_state->has_pch_encoder) {
> > intel_wait_for_vblank(dev_priv, pipe);
> > intel_wait_for_vblank(dev_priv, pipe);
> > }
> > @@ -6591,13 +6590,13 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> > }
> >
> > -static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> > - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> > bool psl_clkgate_wa;
> >
> > if (WARN_ON(crtc->active))
> > @@ -6605,67 +6604,65 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > - if (pipe_config->shared_dpll)
> > - intel_enable_shared_dpll(pipe_config);
> > + if (new_crtc_state->shared_dpll)
> > + intel_enable_shared_dpll(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_set_pipe_timings(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > - icl_enable_trans_port_sync(pipe_config);
> > + icl_enable_trans_port_sync(new_crtc_state);
> >
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > if (cpu_transcoder != TRANSCODER_EDP &&
> > - !transcoder_is_dsi(cpu_transcoder)) {
> > + !transcoder_is_dsi(cpu_transcoder))
> > I915_WRITE(PIPE_MULT(cpu_transcoder),
> > - pipe_config->pixel_multiplier - 1);
> > - }
> > + new_crtc_state->pixel_multiplier - 1);
> >
> > - if (pipe_config->has_pch_encoder) {
> > - intel_cpu_transcoder_set_m_n(pipe_config,
> > - &pipe_config->fdi_m_n, NULL);
> > - }
> > + if (new_crtc_state->has_pch_encoder)
> > + intel_cpu_transcoder_set_m_n(new_crtc_state,
> > + &new_crtc_state->fdi_m_n, NULL);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - haswell_set_pipeconf(pipe_config);
> > + haswell_set_pipeconf(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > - bdw_set_pipemisc(pipe_config);
> > + bdw_set_pipemisc(new_crtc_state);
> >
> > crtc->active = true;
> >
> > /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> > psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > - pipe_config->pch_pfit.enabled;
> > + new_crtc_state->pch_pfit.enabled;
> > if (psl_clkgate_wa)
> > glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
> >
> > if (INTEL_GEN(dev_priv) >= 9)
> > - skylake_pfit_enable(pipe_config);
> > + skylake_pfit_enable(new_crtc_state);
> > else
> > - ironlake_pfit_enable(pipe_config);
> > + ironlake_pfit_enable(new_crtc_state);
> >
> > /*
> > * On ILK+ LUT must be loaded before the pipe is running but with
> > * clocks enabled
> > */
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> > if (INTEL_GEN(dev_priv) < 9)
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_set_pipe_chicken(crtc);
> >
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_ddi_enable_transcoder_func(pipe_config);
> > + intel_ddi_enable_transcoder_func(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > @@ -6675,15 +6672,15 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> > if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - if (pipe_config->has_pch_encoder)
> > - lpt_pch_enable(state, pipe_config);
> > + if (new_crtc_state->has_pch_encoder)
> > + lpt_pch_enable(state, new_crtc_state);
> >
> > - if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> > - intel_ddi_set_vc_payload_alloc(pipe_config, true);
> > + if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DP_MST))
> > + intel_ddi_set_vc_payload_alloc(new_crtc_state, true);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> >
> > @@ -6694,7 +6691,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > /* If we change the relative order between pipe/planes enabling, we need
> > * to change the workaround. */
> > - hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> > + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
> > if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > @@ -7007,28 +7004,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> > intel_display_power_put_unchecked(dev_priv, domain);
> > }
> >
> > -static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > if (WARN_ON(crtc->active))
> > return;
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> > I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> > I915_WRITE(CHV_CANVAS(pipe), 0);
> > }
> >
> > - i9xx_set_pipeconf(pipe_config);
> > + i9xx_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > @@ -7037,26 +7034,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > if (IS_CHERRYVIEW(dev_priv)) {
> > - chv_prepare_pll(crtc, pipe_config);
> > - chv_enable_pll(crtc, pipe_config);
> > + chv_prepare_pll(crtc, new_crtc_state);
> > + chv_enable_pll(crtc, new_crtc_state);
> > } else {
> > - vlv_prepare_pll(crtc, pipe_config);
> > - vlv_enable_pll(crtc, pipe_config);
> > + vlv_prepare_pll(crtc, new_crtc_state);
> > + vlv_enable_pll(crtc, new_crtc_state);
> > }
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - i9xx_pfit_enable(pipe_config);
> > + i9xx_pfit_enable(new_crtc_state);
> >
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > dev_priv->display.initial_watermarks(state, crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> > }
> > @@ -7070,25 +7067,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> > I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> > }
> >
> > -static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> > +static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> > struct intel_atomic_state *state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > if (WARN_ON(crtc->active))
> > return;
> >
> > - i9xx_set_pll_dividers(pipe_config);
> > + i9xx_set_pll_dividers(new_crtc_state);
> >
> > - if (intel_crtc_has_dp_encoder(pipe_config))
> > - intel_dp_set_m_n(pipe_config, M1_N1);
> > + if (intel_crtc_has_dp_encoder(new_crtc_state))
> > + intel_dp_set_m_n(new_crtc_state, M1_N1);
> >
> > - intel_set_pipe_timings(pipe_config);
> > - intel_set_pipe_src_size(pipe_config);
> > + intel_set_pipe_timings(new_crtc_state);
> > + intel_set_pipe_src_size(new_crtc_state);
> >
> > - i9xx_set_pipeconf(pipe_config);
> > + i9xx_set_pipeconf(new_crtc_state);
> >
> > crtc->active = true;
> >
> > @@ -7097,22 +7094,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > - i9xx_enable_pll(crtc, pipe_config);
> > + i9xx_enable_pll(crtc, new_crtc_state);
> >
> > - i9xx_pfit_enable(pipe_config);
> > + i9xx_pfit_enable(new_crtc_state);
> >
> > - intel_color_load_luts(pipe_config);
> > - intel_color_commit(pipe_config);
> > + intel_color_load_luts(new_crtc_state);
> > + intel_color_commit(new_crtc_state);
> > /* update DSPCNTR to configure gamma for pipe bottom color */
> > - intel_disable_primary_plane(pipe_config);
> > + intel_disable_primary_plane(new_crtc_state);
> >
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> > else
> > intel_update_watermarks(crtc);
> > - intel_enable_pipe(pipe_config);
> > + intel_enable_pipe(new_crtc_state);
> >
> > - intel_crtc_vblank_on(pipe_config);
> > + intel_crtc_vblank_on(new_crtc_state);
> >
> > intel_encoders_enable(state, crtc);
> > }
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state+crtc to the .crtc_enable()
.crtc_disable(). Life is easier when you don't have to think
whether to pass the old or the new crtc state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 8 +--
2 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 11953fe06488..96eafd51296c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6460,10 +6460,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6590,10 +6591,11 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -6713,10 +6715,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
}
-static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6769,10 +6772,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -7004,10 +7008,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void valleyview_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7067,10 +7072,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7129,10 +7135,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
I915_WRITE(PFIT_CONTROL, 0);
}
-static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7218,7 +7225,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
WARN_ON(IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
+ dev_priv->display.crtc_disable(to_intel_atomic_state(state),
+ intel_crtc);
drm_atomic_state_put(state);
@@ -14315,7 +14323,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
if (modeset) {
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
@@ -14386,7 +14394,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(old_crtc_state, state);
+ dev_priv->display.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -14501,7 +14509,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
intel_crtc_enable_pipe_crc(crtc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 00fe4ed4fb96..af0c5cd59016 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
- void (*crtc_enable)(struct intel_crtc_state *pipe_config,
- struct intel_atomic_state *old_state);
- void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *old_state);
+ void (*crtc_enable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*crtc_disable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* [Intel-gfx] [PATCH 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-12 14:15 ` Ville Syrjala
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjala @ 2019-11-12 14:15 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state+crtc to the .crtc_enable()
.crtc_disable(). Life is easier when you don't have to think
whether to pass the old or the new crtc state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 8 +--
2 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 11953fe06488..96eafd51296c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6460,10 +6460,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6590,10 +6591,11 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -6713,10 +6715,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
}
-static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6769,10 +6772,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -7004,10 +7008,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void valleyview_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7067,10 +7072,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7129,10 +7135,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
I915_WRITE(PFIT_CONTROL, 0);
}
-static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7218,7 +7225,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
WARN_ON(IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
+ dev_priv->display.crtc_disable(to_intel_atomic_state(state),
+ intel_crtc);
drm_atomic_state_put(state);
@@ -14315,7 +14323,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
if (modeset) {
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
@@ -14386,7 +14394,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(old_crtc_state, state);
+ dev_priv->display.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -14501,7 +14509,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
intel_crtc_enable_pipe_crc(crtc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 00fe4ed4fb96..af0c5cd59016 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
- void (*crtc_enable)(struct intel_crtc_state *pipe_config,
- struct intel_atomic_state *old_state);
- void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *old_state);
+ void (*crtc_enable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*crtc_disable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-14 0:37 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic state+crtc to the .crtc_enable()
> .crtc_disable(). Life is easier when you don't have to think
> whether to pass the old or the new crtc state.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
makes total sens and indeed easier life,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 8 +--
> 2 files changed, 37 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 11953fe06488..96eafd51296c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6460,10 +6460,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> plane->disable_plane(plane, crtc_state);
> }
>
> -static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void ironlake_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6590,10 +6591,11 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
>
> -static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void haswell_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> @@ -6713,10 +6715,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> }
> }
>
> -static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void ironlake_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6769,10 +6772,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> }
>
> -static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void haswell_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> @@ -7004,10 +7008,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> intel_display_power_put_unchecked(dev_priv, domain);
> }
>
> -static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void valleyview_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7067,10 +7072,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> }
>
> -static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void i9xx_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7129,10 +7135,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> I915_WRITE(PFIT_CONTROL, 0);
> }
>
> -static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void i9xx_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7218,7 +7225,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
>
> WARN_ON(IS_ERR(temp_crtc_state) || ret);
>
> - dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
> + dev_priv->display.crtc_disable(to_intel_atomic_state(state),
> + intel_crtc);
>
> drm_atomic_state_put(state);
>
> @@ -14315,7 +14323,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> if (modeset) {
> intel_crtc_update_active_timings(new_crtc_state);
>
> - dev_priv->display.crtc_enable(new_crtc_state, state);
> + dev_priv->display.crtc_enable(state, crtc);
>
> /* vblanks work again, re-enable pipe CRC. */
> intel_crtc_enable_pipe_crc(crtc);
> @@ -14386,7 +14394,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> */
> intel_crtc_disable_pipe_crc(crtc);
>
> - dev_priv->display.crtc_disable(old_crtc_state, state);
> + dev_priv->display.crtc_disable(state, crtc);
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
> @@ -14501,7 +14509,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> intel_crtc_update_active_timings(new_crtc_state);
> - dev_priv->display.crtc_enable(new_crtc_state, state);
> + dev_priv->display.crtc_enable(state, crtc);
> intel_crtc_enable_pipe_crc(crtc);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 00fe4ed4fb96..af0c5cd59016 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
> struct intel_initial_plane_config *);
> int (*crtc_compute_clock)(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> - void (*crtc_enable)(struct intel_crtc_state *pipe_config,
> - struct intel_atomic_state *old_state);
> - void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *old_state);
> + void (*crtc_enable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*crtc_disable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void (*commit_modeset_enables)(struct intel_atomic_state *state);
> void (*commit_modeset_disables)(struct intel_atomic_state *state);
> void (*audio_codec_enable)(struct intel_encoder *encoder,
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [Intel-gfx] [PATCH 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-14 0:37 ` Manasi Navare
0 siblings, 0 replies; 50+ messages in thread
From: Manasi Navare @ 2019-11-14 0:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Nov 12, 2019 at 04:15:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just pass the atomic state+crtc to the .crtc_enable()
> .crtc_disable(). Life is easier when you don't have to think
> whether to pass the old or the new crtc state.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
makes total sens and indeed easier life,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 8 +--
> 2 files changed, 37 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 11953fe06488..96eafd51296c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6460,10 +6460,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> plane->disable_plane(plane, crtc_state);
> }
>
> -static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void ironlake_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6590,10 +6591,11 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
>
> -static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void haswell_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> @@ -6713,10 +6715,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> }
> }
>
> -static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void ironlake_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6769,10 +6772,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> }
>
> -static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void haswell_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> @@ -7004,10 +7008,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> intel_display_power_put_unchecked(dev_priv, domain);
> }
>
> -static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void valleyview_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7067,10 +7072,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
> }
>
> -static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
> - struct intel_atomic_state *state)
> +static void i9xx_crtc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7129,10 +7135,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> I915_WRITE(PFIT_CONTROL, 0);
> }
>
> -static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *state)
> +static void i9xx_crtc_disable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> + struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7218,7 +7225,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
>
> WARN_ON(IS_ERR(temp_crtc_state) || ret);
>
> - dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
> + dev_priv->display.crtc_disable(to_intel_atomic_state(state),
> + intel_crtc);
>
> drm_atomic_state_put(state);
>
> @@ -14315,7 +14323,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> if (modeset) {
> intel_crtc_update_active_timings(new_crtc_state);
>
> - dev_priv->display.crtc_enable(new_crtc_state, state);
> + dev_priv->display.crtc_enable(state, crtc);
>
> /* vblanks work again, re-enable pipe CRC. */
> intel_crtc_enable_pipe_crc(crtc);
> @@ -14386,7 +14394,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> */
> intel_crtc_disable_pipe_crc(crtc);
>
> - dev_priv->display.crtc_disable(old_crtc_state, state);
> + dev_priv->display.crtc_disable(state, crtc);
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
> @@ -14501,7 +14509,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>
> intel_crtc_update_active_timings(new_crtc_state);
> - dev_priv->display.crtc_enable(new_crtc_state, state);
> + dev_priv->display.crtc_enable(state, crtc);
> intel_crtc_enable_pipe_crc(crtc);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 00fe4ed4fb96..af0c5cd59016 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
> struct intel_initial_plane_config *);
> int (*crtc_compute_clock)(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> - void (*crtc_enable)(struct intel_crtc_state *pipe_config,
> - struct intel_atomic_state *old_state);
> - void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
> - struct intel_atomic_state *old_state);
> + void (*crtc_enable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*crtc_disable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void (*commit_modeset_enables)(struct intel_atomic_state *state);
> void (*commit_modeset_disables)(struct intel_atomic_state *state);
> void (*audio_codec_enable)(struct intel_encoder *encoder,
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Cleanups around .crtc_enable/disable()
@ 2019-11-12 15:37 ` Patchwork
0 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2019-11-12 15:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable()
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7316 -> Patchwork_15234
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15234 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15234, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15234:
### IGT changes ###
#### Possible regressions ####
* igt@prime_vgem@basic-sync-default:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-bdw-5557u/igt@prime_vgem@basic-sync-default.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-bdw-5557u/igt@prime_vgem@basic-sync-default.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_15234 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gtt:
- fi-skl-6600u: [PASS][5] -> [TIMEOUT][6] ([fdo#111732 ])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-skl-6600u/igt@i915_selftest@live_gtt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-skl-6600u/igt@i915_selftest@live_gtt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111407])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-6770hq: [PASS][9] -> [WARN][10] ([fdo#112252])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770: [SKIP][11] ([fdo#109271]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live_execlists:
- {fi-kbl-7560u}: [INCOMPLETE][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7316/fi-kbl-7560u/igt@i915_selftest@live_execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/fi-kbl-7560u/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111732 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
[fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
Participating hosts (52 -> 45)
------------------------------
Additional (1): fi-gdg-551
Missing (8): fi-hsw-4770r fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7316 -> Patchwork_15234
CI-20190529: 20190529
CI_DRM_7316: a4939708275196364ef98691a90c89d501536494 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5272: 5997df31db10f190fe8b70d920b6a6b8d3b24126 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15234: 9899c3878df3b2492027074eca2fa393a9bd0849 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9899c3878df3 drm/i915: Change .crtc_enable/disable() calling convention
657718a9bff8 drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
3b0a98a39380 drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
4f42f6bd0ad8 drm/i915: Pass dev_priv to cpt_verify_modeset()
d9b9783cb2c1 drm/i915: Change watermark hook calling convention
4c3c2c84bc0e drm/i915: Pass intel_crtc to ironlake_fdi_disable()
eb07996bb329 drm/i915: Move crtc_state to tighter scope
1c3890f77ce2 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
e986dc329135 drm/i915: Add intel_crtc_vblank_off()
12564e30176b drm/i915: Change intel_encoders_<hook>() calling convention
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15234/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread* ✗ Fi.CI.BUILD: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev2)
@ 2019-11-15 21:36 ` Patchwork
0 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2019-11-15 21:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev2)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
Applying: drm/i915: Change intel_encoders_<hook>() calling convention
Applying: drm/i915: Add intel_crtc_vblank_off()
Applying: drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev2)
@ 2019-11-15 21:36 ` Patchwork
0 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2019-11-15 21:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev2)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
Applying: drm/i915: Change intel_encoders_<hook>() calling convention
Applying: drm/i915: Add intel_crtc_vblank_off()
Applying: drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread