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From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	haitao.suo@bitmain.com, darren.tsao@bitmain.com,
	fisher.cheng@bitmain.com, alec.lin@bitmain.com
Subject: Re: [PATCH v6 0/7] Add Bitmain BM1880 clock driver
Date: Wed, 13 Nov 2019 21:50:53 -0800	[thread overview]
Message-ID: <20191114055054.C280F206DA@mail.kernel.org> (raw)
In-Reply-To: <20191114053404.GA8459@mani>

Quoting Manivannan Sadhasivam (2019-11-13 21:34:04)
> On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> > > Hello,
> > > 
> > > This patchset adds common clock driver for Bitmain BM1880 SoC clock
> > > controller. The clock controller consists of gate, divider, mux
> > > and pll clocks with different compositions. Hence, the driver uses
> > > composite clock structure in place where multiple clocking units are
> > > combined together.
> > > 
> > > This patchset also removes UART fixed clock and sources clocks from clock
> > > controller for Sophon Edge board where the driver has been validated.
> > > 
> > 
> > Are you waiting for review here? I see some kbuild reports so I assumed
> > you would fix and resend.
> 
> I'll fix it but I was expecting some review from you so that I can send the
> next revision incorporating all comments.
> 

Ok. I'm glad I broke the silence then.

Can you please resend without any dts changes? Those don't go through
clk tree. I think otherwise the patches look OK, although I was hoping
you could register clks by using the new way of specifying parents. Is
that possible?


WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: devicetree@vger.kernel.org, mturquette@baylibre.com,
	linux-kernel@vger.kernel.org, darren.tsao@bitmain.com,
	robh+dt@kernel.org, haitao.suo@bitmain.com,
	fisher.cheng@bitmain.com, alec.lin@bitmain.com,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 0/7] Add Bitmain BM1880 clock driver
Date: Wed, 13 Nov 2019 21:50:53 -0800	[thread overview]
Message-ID: <20191114055054.C280F206DA@mail.kernel.org> (raw)
In-Reply-To: <20191114053404.GA8459@mani>

Quoting Manivannan Sadhasivam (2019-11-13 21:34:04)
> On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> > > Hello,
> > > 
> > > This patchset adds common clock driver for Bitmain BM1880 SoC clock
> > > controller. The clock controller consists of gate, divider, mux
> > > and pll clocks with different compositions. Hence, the driver uses
> > > composite clock structure in place where multiple clocking units are
> > > combined together.
> > > 
> > > This patchset also removes UART fixed clock and sources clocks from clock
> > > controller for Sophon Edge board where the driver has been validated.
> > > 
> > 
> > Are you waiting for review here? I see some kbuild reports so I assumed
> > you would fix and resend.
> 
> I'll fix it but I was expecting some review from you so that I can send the
> next revision incorporating all comments.
> 

Ok. I'm glad I broke the silence then.

Can you please resend without any dts changes? Those don't go through
clk tree. I think otherwise the patches look OK, although I was hoping
you could register clks by using the new way of specifying parents. Is
that possible?


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  reply	other threads:[~2019-11-14  5:50 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-26 11:02 [PATCH v6 0/7] Add Bitmain BM1880 clock driver Manivannan Sadhasivam
2019-10-26 11:02 ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 1/7] clk: Zero init clk_init_data in helpers Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 2/7] clk: Add clk_hw_unregister_composite helper function definition Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 3/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 4/7] arm64: dts: bitmain: Add clock controller support " Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 5/7] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-26 11:02 ` [PATCH v6 6/7] clk: Add common clock driver for BM1880 SoC Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-10-29  9:01   ` kbuild test robot
2019-10-29  9:01     ` kbuild test robot
2019-10-29  9:01     ` kbuild test robot
2019-10-30  3:44   ` kbuild test robot
2019-10-30  3:44     ` kbuild test robot
2019-10-26 11:02 ` [PATCH v6 7/7] MAINTAINERS: Add entry for BM1880 SoC clock driver Manivannan Sadhasivam
2019-10-26 11:02   ` Manivannan Sadhasivam
2019-11-13 22:21 ` [PATCH v6 0/7] Add Bitmain BM1880 " Stephen Boyd
2019-11-13 22:21   ` Stephen Boyd
2019-11-14  5:34   ` Manivannan Sadhasivam
2019-11-14  5:34     ` Manivannan Sadhasivam
2019-11-14  5:50     ` Stephen Boyd [this message]
2019-11-14  5:50       ` Stephen Boyd
2019-11-14  6:09       ` Manivannan Sadhasivam
2019-11-14  6:09         ` Manivannan Sadhasivam

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