* [PATCH 0/3] Wa_1604555607 implementation and verification skip
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
Implements the Wa_1604555607 and skips its verification as the FF_MODES2
register is writeonly till TGL B0.
Test-with: 20191120145712.27496-1-ramalingam.c@intel.com
Michel Thierry (1):
drm/i915/tgl: Implement Wa_1604555607
Ramalingam C (2):
drm/i915: marking readability of WA registers
drm/i915: Skip the Wa_1604555607 verification
drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 ++
2 files changed, 32 insertions(+), 15 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 0/3] Wa_1604555607 implementation and verification skip
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
Implements the Wa_1604555607 and skips its verification as the FF_MODES2
register is writeonly till TGL B0.
Test-with: 20191120145712.27496-1-ramalingam.c@intel.com
Michel Thierry (1):
drm/i915/tgl: Implement Wa_1604555607
Ramalingam C (2):
drm/i915: marking readability of WA registers
drm/i915: Skip the Wa_1604555607 verification
drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 ++
2 files changed, 32 insertions(+), 15 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
uncore read is used [Tvrtko]
Macros as used for MASK definition [Chris]
BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..0fc383814ef2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,9 +568,17 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ u32 val;
+
/* Wa_1409142259:tgl */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+ /* Wa_1604555607:tgl */
+ val = intel_uncore_read(engine->uncore, FF_MODE2);
+ val &= ~FF_MODE2_TDS_TIMER_MASK;
+ val |= FF_MODE2_TDS_TIMER_128;
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
+#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
/* PCH */
#define PCH_DISPLAY_BASE 0xc0000u
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
uncore read is used [Tvrtko]
Macros as used for MASK definition [Chris]
BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..0fc383814ef2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,9 +568,17 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ u32 val;
+
/* Wa_1409142259:tgl */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+ /* Wa_1604555607:tgl */
+ val = intel_uncore_read(engine->uncore, FF_MODE2);
+ val &= ~FF_MODE2_TDS_TIMER_MASK;
+ val |= FF_MODE2_TDS_TIMER_128;
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
+#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
/* PCH */
#define PCH_DISPLAY_BASE 0xc0000u
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] drm/i915: marking readability of WA registers
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
WA infrastructure is extended to record the WA register readability for
verification purpose.
With this, if a WA register is not readable for any reasons,
verification will be skipped for that WA.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 +++++++++++----------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0fc383814ef2..8c441bf10cb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -148,13 +148,13 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
static void
wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
+ u32 val, bool readable)
{
struct i915_wa wa = {
.reg = reg,
.mask = mask,
.val = val,
- .read = mask,
+ .read = readable ? mask : 0,
};
_wa_add(wal, &wa);
@@ -163,29 +163,30 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
+ wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val), true);
}
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, ~0, val);
+ wa_write_masked_or(wal, reg, ~0, val, true);
}
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, val);
+ wa_write_masked_or(wal, reg, val, val, true);
}
#define WA_SET_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask), true)
#define WA_CLR_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask), true)
#define WA_SET_FIELD_MASKED(addr, mask, value) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), \
+ (value)), true)
static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
@@ -553,7 +554,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_write_masked_or(wal,
GEN10_CACHE_MODE_SS,
0, /* write-only, so skip validation */
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
+ true);
/* WaDisableGPGPUMidThreadPreemption:icl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
@@ -827,7 +829,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
- wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+ wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr, true);
}
static void
@@ -861,7 +863,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_GACB_PERF_CTRL,
GEN11_HASH_CTRL_MASK,
- GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4, true);
/* Wa_1405766107:icl
* Formerly known as WaCL2SFHalfMaxAlloc
@@ -1359,11 +1361,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN8_GARBCNTL,
GEN11_HASH_CTRL_EXCL_MASK,
- GEN11_HASH_CTRL_EXCL_BIT0);
+ GEN11_HASH_CTRL_EXCL_BIT0, true);
wa_write_masked_or(wal,
GEN11_GLBLINVL,
GEN11_BANK_HASH_ADDR_EXCL_MASK,
- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0, true);
/*
* Wa_1405733216:icl
@@ -1395,7 +1397,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_SCRATCH2,
GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ 0, true);
}
if (IS_GEN_RANGE(i915, 9, 11)) {
@@ -1436,7 +1438,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN8_L3SQCREG1,
L3_PRIO_CREDITS_MASK,
L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ L3_HIGH_PRIO_CREDITS(2), true);
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
wa_write_or(wal,
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: marking readability of WA registers
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
WA infrastructure is extended to record the WA register readability for
verification purpose.
With this, if a WA register is not readable for any reasons,
verification will be skipped for that WA.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 +++++++++++----------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0fc383814ef2..8c441bf10cb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -148,13 +148,13 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
static void
wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
+ u32 val, bool readable)
{
struct i915_wa wa = {
.reg = reg,
.mask = mask,
.val = val,
- .read = mask,
+ .read = readable ? mask : 0,
};
_wa_add(wal, &wa);
@@ -163,29 +163,30 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
+ wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val), true);
}
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, ~0, val);
+ wa_write_masked_or(wal, reg, ~0, val, true);
}
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, val);
+ wa_write_masked_or(wal, reg, val, val, true);
}
#define WA_SET_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask), true)
#define WA_CLR_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask), true)
#define WA_SET_FIELD_MASKED(addr, mask, value) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), \
+ (value)), true)
static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
@@ -553,7 +554,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_write_masked_or(wal,
GEN10_CACHE_MODE_SS,
0, /* write-only, so skip validation */
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
+ true);
/* WaDisableGPGPUMidThreadPreemption:icl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
@@ -827,7 +829,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
- wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+ wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr, true);
}
static void
@@ -861,7 +863,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_GACB_PERF_CTRL,
GEN11_HASH_CTRL_MASK,
- GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4, true);
/* Wa_1405766107:icl
* Formerly known as WaCL2SFHalfMaxAlloc
@@ -1359,11 +1361,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN8_GARBCNTL,
GEN11_HASH_CTRL_EXCL_MASK,
- GEN11_HASH_CTRL_EXCL_BIT0);
+ GEN11_HASH_CTRL_EXCL_BIT0, true);
wa_write_masked_or(wal,
GEN11_GLBLINVL,
GEN11_BANK_HASH_ADDR_EXCL_MASK,
- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0, true);
/*
* Wa_1405733216:icl
@@ -1395,7 +1397,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_SCRATCH2,
GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ 0, true);
}
if (IS_GEN_RANGE(i915, 9, 11)) {
@@ -1436,7 +1438,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN8_L3SQCREG1,
L3_PRIO_CREDITS_MASK,
L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ L3_HIGH_PRIO_CREDITS(2), true);
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
wa_write_or(wal,
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8c441bf10cb1..0a3034e841c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
- wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
+ /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+ !IS_TGL_REVID(engine->uncore->i915, 0,
+ TGL_REVID_A0));
}
static void
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 16:40 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 16:40 UTC (permalink / raw)
To: intel-gfx
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8c441bf10cb1..0a3034e841c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
- wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
+ /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+ !IS_TGL_REVID(engine->uncore->i915, 0,
+ TGL_REVID_A0));
}
static void
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 16:55 ` Tvrtko Ursulin
0 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-11-20 16:55 UTC (permalink / raw)
To: Ramalingam C, intel-gfx
On 20/11/2019 16:40, Ramalingam C wrote:
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 8c441bf10cb1..0a3034e841c4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> val = intel_uncore_read(engine->uncore, FF_MODE2);
> val &= ~FF_MODE2_TDS_TIMER_MASK;
> val |= FF_MODE2_TDS_TIMER_128;
> - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> + /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> + !IS_TGL_REVID(engine->uncore->i915, 0,
> + TGL_REVID_A0));
Why do you need the previous patch and can't just re-add the helper (we
had it at some point) which creates the workaround with wa->read = 0
directly?
wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
explicitly passed in?
Regards,
Tvrtko
> }
>
> static void
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 16:55 ` Tvrtko Ursulin
0 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-11-20 16:55 UTC (permalink / raw)
To: Ramalingam C, intel-gfx
On 20/11/2019 16:40, Ramalingam C wrote:
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 8c441bf10cb1..0a3034e841c4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> val = intel_uncore_read(engine->uncore, FF_MODE2);
> val &= ~FF_MODE2_TDS_TIMER_MASK;
> val |= FF_MODE2_TDS_TIMER_128;
> - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> + /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> + !IS_TGL_REVID(engine->uncore->i915, 0,
> + TGL_REVID_A0));
Why do you need the previous patch and can't just re-add the helper (we
had it at some point) which creates the workaround with wa->read = 0
directly?
wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
explicitly passed in?
Regards,
Tvrtko
> }
>
> static void
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 17:33 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 17:33 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On 2019-11-20 at 16:55:35 +0000, Tvrtko Ursulin wrote:
>
> On 20/11/2019 16:40, Ramalingam C wrote:
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> >
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 8c441bf10cb1..0a3034e841c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > val = intel_uncore_read(engine->uncore, FF_MODE2);
> > val &= ~FF_MODE2_TDS_TIMER_MASK;
> > val |= FF_MODE2_TDS_TIMER_128;
> > - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> > + /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > + !IS_TGL_REVID(engine->uncore->i915, 0,
> > + TGL_REVID_A0));
>
> Why do you need the previous patch and can't just re-add the helper (we had
> it at some point) which creates the workaround with wa->read = 0 directly?
>
> wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
> explicitly passed in?
Thanks Tvrtko. That helped to avoid many changes across file.
implemented wa_write_masked_or__no_verify
-Ram
>
> Regards,
>
> Tvrtko
>
> > }
> > static void
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification
@ 2019-11-20 17:33 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2019-11-20 17:33 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On 2019-11-20 at 16:55:35 +0000, Tvrtko Ursulin wrote:
>
> On 20/11/2019 16:40, Ramalingam C wrote:
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> >
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 8c441bf10cb1..0a3034e841c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > val = intel_uncore_read(engine->uncore, FF_MODE2);
> > val &= ~FF_MODE2_TDS_TIMER_MASK;
> > val |= FF_MODE2_TDS_TIMER_128;
> > - wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> > + /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> > + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > + !IS_TGL_REVID(engine->uncore->i915, 0,
> > + TGL_REVID_A0));
>
> Why do you need the previous patch and can't just re-add the helper (we had
> it at some point) which creates the workaround with wa->read = 0 directly?
>
> wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
> explicitly passed in?
Thanks Tvrtko. That helped to avoid many changes across file.
implemented wa_write_masked_or__no_verify
-Ram
>
> Regards,
>
> Tvrtko
>
> > }
> > static void
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-11-20 17:34 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-11-20 16:40 [PATCH 0/3] Wa_1604555607 implementation and verification skip Ramalingam C
2019-11-20 16:40 ` [Intel-gfx] " Ramalingam C
2019-11-20 16:40 ` [PATCH 1/3] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
2019-11-20 16:40 ` [Intel-gfx] " Ramalingam C
2019-11-20 16:40 ` [PATCH 2/3] drm/i915: marking readability of WA registers Ramalingam C
2019-11-20 16:40 ` [Intel-gfx] " Ramalingam C
2019-11-20 16:40 ` [PATCH 3/3] drm/i915: Skip the Wa_1604555607 verification Ramalingam C
2019-11-20 16:40 ` [Intel-gfx] " Ramalingam C
2019-11-20 16:55 ` Tvrtko Ursulin
2019-11-20 16:55 ` [Intel-gfx] " Tvrtko Ursulin
2019-11-20 17:33 ` Ramalingam C
2019-11-20 17:33 ` [Intel-gfx] " Ramalingam C
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