From: Stephen Boyd <sboyd@kernel.org>
To: linux-aspeed@lists.ozlabs.org
Subject: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
Date: Tue, 26 Nov 2019 10:03:19 -0800 [thread overview]
Message-ID: <20191126180320.1A2132071A@mail.kernel.org> (raw)
In-Reply-To: <20191010020655.3776-3-andrew@aj.id.au>
Quoting Andrew Jeffery (2019-10-09 19:06:55)
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
Applied to clk-next
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Andrew Jeffery <andrew@aj.id.au>, linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, joel@jms.id.au, robh+dt@kernel.org,
mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
Date: Tue, 26 Nov 2019 10:03:19 -0800 [thread overview]
Message-ID: <20191126180320.1A2132071A@mail.kernel.org> (raw)
In-Reply-To: <20191010020655.3776-3-andrew@aj.id.au>
Quoting Andrew Jeffery (2019-10-09 19:06:55)
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
Applied to clk-next
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Andrew Jeffery <andrew@aj.id.au>, linux-clk@vger.kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-aspeed@lists.ozlabs.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, joel@jms.id.au,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
Date: Tue, 26 Nov 2019 10:03:19 -0800 [thread overview]
Message-ID: <20191126180320.1A2132071A@mail.kernel.org> (raw)
In-Reply-To: <20191010020655.3776-3-andrew@aj.id.au>
Quoting Andrew Jeffery (2019-10-09 19:06:55)
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
Applied to clk-next
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next prev parent reply other threads:[~2019-11-26 18:03 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-10 2:06 [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 23:39 ` Joel Stanley
2019-10-10 23:39 ` Joel Stanley
2019-10-10 23:39 ` Joel Stanley
2019-10-11 17:01 ` Rob Herring
2019-10-11 17:01 ` Rob Herring
2019-10-11 17:01 ` Rob Herring
2019-10-10 2:06 ` [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 2:06 ` Andrew Jeffery
2019-10-10 23:41 ` Joel Stanley
2019-10-10 23:41 ` Joel Stanley
2019-10-10 23:41 ` Joel Stanley
2019-11-26 0:59 ` Joel Stanley
2019-11-26 0:59 ` Joel Stanley
2019-11-26 0:59 ` Joel Stanley
2019-11-26 18:01 ` Stephen Boyd
2019-11-26 18:01 ` Stephen Boyd
2019-11-26 18:01 ` Stephen Boyd
2019-11-26 18:03 ` Stephen Boyd [this message]
2019-11-26 18:03 ` Stephen Boyd
2019-11-26 18:03 ` Stephen Boyd
2019-11-29 1:22 ` Joel Stanley
2019-11-29 1:22 ` Joel Stanley
2019-11-29 1:22 ` Joel Stanley
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