From: Christoph Hellwig <hch@lst.de>
To: Keith Busch <kbusch@kernel.org>
Cc: sagi@grimberg.me, bigeasy@linutronix.de,
linux-nvme@lists.infradead.org, ming.lei@redhat.com,
helgaas@kernel.org, hch@lst.de
Subject: Re: [PATCH 3/4] nvme/pci: Mask MSIx interrupts for threaded handling
Date: Thu, 28 Nov 2019 08:19:59 +0100 [thread overview]
Message-ID: <20191128071959.GB20330@lst.de> (raw)
In-Reply-To: <20191127175824.1929-4-kbusch@kernel.org>
On Thu, Nov 28, 2019 at 02:58:23AM +0900, Keith Busch wrote:
> The nvme irq thread, when enabled, may run for a while as new completions
> are submitted. These completions may also send MSI messages, which could
> be detected as spurious and disables the nvme irq.
>
> Use the fast MSIx mask to disable the controller from sending MSIx
> interrupts while the nvme bottom half thread is running.
I thin kwe should keep this together with patch 2, not just in the
patch series but also in the code - I'd rather have two little helper
to enable/disable an irq with if for the two cases and a good comment
right next to that than splitting the higher level functions.
_______________________________________________
linux-nvme mailing list
linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme
next prev parent reply other threads:[~2019-11-28 7:20 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-27 17:58 [PATCH 0/4] nvme: Threaded interrupt handling improvements Keith Busch
2019-11-27 17:58 ` [PATCH 1/4] PCI/MSI: Export __pci_msix_desc_mask_irq Keith Busch
2019-11-28 2:42 ` Sagi Grimberg
2019-11-28 3:41 ` Keith Busch
2019-11-28 7:17 ` Christoph Hellwig
2019-11-27 17:58 ` [PATCH 2/4] nvme/pci: Mask legacy and MSI in threaded handler Keith Busch
2019-11-28 3:39 ` Ming Lei
2019-11-28 3:48 ` Keith Busch
2019-11-28 3:58 ` Ming Lei
2019-11-28 4:14 ` Keith Busch
2019-11-28 8:41 ` Ming Lei
2019-11-27 17:58 ` [PATCH 3/4] nvme/pci: Mask MSIx interrupts for threaded handling Keith Busch
2019-11-28 7:19 ` Christoph Hellwig [this message]
2019-11-27 17:58 ` [PATCH 4/4] nvme/pci: Spin threaded interrupt completions Keith Busch
2019-11-28 2:46 ` Sagi Grimberg
2019-11-28 3:28 ` Keith Busch
2019-11-28 3:51 ` Ming Lei
2019-11-28 3:58 ` Keith Busch
2019-11-28 7:22 ` Christoph Hellwig
2019-11-29 9:13 ` Sebastian Andrzej Siewior
2019-11-30 18:10 ` Keith Busch
2019-12-02 1:10 ` Ming Lei
2019-12-02 1:30 ` Keith Busch
2019-12-02 16:51 ` Sebastian Andrzej Siewior
2019-11-28 7:50 ` [PATCH 0/4] nvme: Threaded interrupt handling improvements Christoph Hellwig
2019-11-28 17:59 ` Keith Busch
2019-11-29 8:30 ` Christoph Hellwig
2019-11-29 9:46 ` Sebastian Andrzej Siewior
2019-11-29 16:27 ` Keith Busch
2019-11-29 17:05 ` Sebastian Andrzej Siewior
2019-11-30 17:02 ` Keith Busch
2019-12-02 17:05 ` Sebastian Andrzej Siewior
2019-12-02 17:12 ` Christoph Hellwig
2019-12-02 18:06 ` Keith Busch
2019-12-03 7:40 ` Christoph Hellwig
2019-12-02 19:57 ` Sebastian Andrzej Siewior
2019-12-03 7:42 ` Christoph Hellwig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191128071959.GB20330@lst.de \
--to=hch@lst.de \
--cc=bigeasy@linutronix.de \
--cc=helgaas@kernel.org \
--cc=kbusch@kernel.org \
--cc=linux-nvme@lists.infradead.org \
--cc=ming.lei@redhat.com \
--cc=sagi@grimberg.me \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.