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From: Marc Zyngier <maz@kernel.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	kvmarm@lists.cs.columbia.edu
Subject: [PATCH v2 0/5] target/arm: More EL2 trapping fixes
Date: Sun,  1 Dec 2019 12:20:13 +0000	[thread overview]
Message-ID: <20191201122018.25808-1-maz@kernel.org> (raw)

Hi all,

This series is a follow-up on [1], which tried to address the
remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed the
comments that Peter and Edgar raised.

I've also tried to tackle missing traps generated by HSTR_EL2, which
got completely ignored so far. Note that this results in the use of a
new TB bit, which I understand is a rare resource. I'd welcome
comments on how to handle it differently if at all possible.

Finally, and as a bonus non-feature, I've added support for the
missing Jazelle registers, giving me the opportunity to allow trapping
of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)

I'm now going back to kernel stuff. I swear!

[1] https://patchew.org/QEMU/20191128161718.24361-1-maz@kernel.org/

Marc Zyngier (5):
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Add support for missing Jazelle system registers

 target/arm/cpu.h               |   2 +
 target/arm/helper-a64.h        |   2 +
 target/arm/helper.c            | 100 ++++++++++++++++++++++++++++++---
 target/arm/op_helper.c         |  21 +++++++
 target/arm/translate-vfp.inc.c |  18 +++++-
 target/arm/translate.c         |   3 +-
 target/arm/translate.h         |   2 +
 target/arm/vfp_helper.c        |  29 ++++++++++
 8 files changed, 165 insertions(+), 12 deletions(-)

-- 
2.20.1

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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	kvmarm@lists.cs.columbia.edu
Subject: [PATCH v2 0/5] target/arm: More EL2 trapping fixes
Date: Sun,  1 Dec 2019 12:20:13 +0000	[thread overview]
Message-ID: <20191201122018.25808-1-maz@kernel.org> (raw)

Hi all,

This series is a follow-up on [1], which tried to address the
remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed the
comments that Peter and Edgar raised.

I've also tried to tackle missing traps generated by HSTR_EL2, which
got completely ignored so far. Note that this results in the use of a
new TB bit, which I understand is a rare resource. I'd welcome
comments on how to handle it differently if at all possible.

Finally, and as a bonus non-feature, I've added support for the
missing Jazelle registers, giving me the opportunity to allow trapping
of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)

I'm now going back to kernel stuff. I swear!

[1] https://patchew.org/QEMU/20191128161718.24361-1-maz@kernel.org/

Marc Zyngier (5):
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Add support for missing Jazelle system registers

 target/arm/cpu.h               |   2 +
 target/arm/helper-a64.h        |   2 +
 target/arm/helper.c            | 100 ++++++++++++++++++++++++++++++---
 target/arm/op_helper.c         |  21 +++++++
 target/arm/translate-vfp.inc.c |  18 +++++-
 target/arm/translate.c         |   3 +-
 target/arm/translate.h         |   2 +
 target/arm/vfp_helper.c        |  29 ++++++++++
 8 files changed, 165 insertions(+), 12 deletions(-)

-- 
2.20.1



             reply	other threads:[~2019-12-01 12:20 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-01 12:20 Marc Zyngier [this message]
2019-12-01 12:20 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Marc Zyngier
2019-12-01 12:20 ` [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Marc Zyngier
2019-12-01 12:20   ` Marc Zyngier
2019-12-02 13:52   ` Edgar E. Iglesias
2019-12-02 13:52     ` Edgar E. Iglesias
2019-12-02 15:10   ` Richard Henderson
2019-12-02 15:10     ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 " Marc Zyngier
2019-12-01 12:20   ` Marc Zyngier
2019-12-02 15:22   ` Richard Henderson
2019-12-02 15:22     ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Marc Zyngier
2019-12-01 12:20   ` Marc Zyngier
2019-12-02 15:35   ` Richard Henderson
2019-12-02 15:35     ` Richard Henderson
2019-12-02 16:45     ` Marc Zyngier
2019-12-02 16:45       ` Marc Zyngier
2019-12-02 16:56       ` Richard Henderson
2019-12-02 16:56         ` Richard Henderson
2019-12-02 17:15         ` Marc Zyngier
2019-12-02 17:15           ` Marc Zyngier
2019-12-06 14:08   ` Peter Maydell
2019-12-06 14:08     ` Peter Maydell
2019-12-06 14:14     ` Marc Zyngier
2019-12-06 14:14       ` Marc Zyngier
2019-12-06 17:45     ` Richard Henderson
2019-12-06 17:45       ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Marc Zyngier
2019-12-01 12:20   ` Marc Zyngier
2019-12-02 15:52   ` Richard Henderson
2019-12-02 15:52     ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Marc Zyngier
2019-12-01 12:20   ` Marc Zyngier
2019-12-02 14:07   ` Edgar E. Iglesias
2019-12-02 14:07     ` Edgar E. Iglesias
2019-12-02 15:57   ` Richard Henderson
2019-12-02 15:57     ` Richard Henderson
2019-12-06 13:56     ` Peter Maydell
2019-12-06 13:56       ` Peter Maydell
2019-12-06 14:13 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Peter Maydell
2019-12-06 14:13   ` Peter Maydell
2019-12-06 14:19   ` Marc Zyngier
2019-12-06 14:19     ` Marc Zyngier

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