[PATCH 0/7] drm/i915: Cleanups around pre/post plane update

[PATCH 0/7] drm/i915: Cleanups around pre/post plane update

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I was poking around the fbc stuff and again stumbled on the
mess in intel_{pre,post}_plane_update(), so I proceeded to
clean it up a bit.

Ville Syrjälä (7):
  drm/i915: Clean up arguments to nv12/scaler w/a funcs
  drm/i915: Pass dev_priv to ilk_disable_lp_wm()
  drm/i915: s/pipe_config/new_crtc_state/
    intel_{pre,post}_plane_update()
  drm/i915: Clean up intel_{pre,post}_plane_update()
  drm/i915: Clean up the gen2 "no planes -> underrun" workaround
  drm/i915: Nuke intel_pre_disable_primary_noatomic()
  drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

 drivers/gpu/drm/i915/display/intel_display.c | 316 +++++++++----------
 drivers/gpu/drm/i915/display/intel_fbc.c     |  14 +-
 drivers/gpu/drm/i915/display/intel_fbc.h     |   8 +-
 drivers/gpu/drm/i915/intel_pm.c              |   4 +-
 drivers/gpu/drm/i915/intel_pm.h              |   2 +-
 5 files changed, 154 insertions(+), 190 deletions(-)

-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 0/7] drm/i915: Cleanups around pre/post plane update

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I was poking around the fbc stuff and again stumbled on the
mess in intel_{pre,post}_plane_update(), so I proceeded to
clean it up a bit.

Ville Syrjälä (7):
  drm/i915: Clean up arguments to nv12/scaler w/a funcs
  drm/i915: Pass dev_priv to ilk_disable_lp_wm()
  drm/i915: s/pipe_config/new_crtc_state/
    intel_{pre,post}_plane_update()
  drm/i915: Clean up intel_{pre,post}_plane_update()
  drm/i915: Clean up the gen2 "no planes -> underrun" workaround
  drm/i915: Nuke intel_pre_disable_primary_noatomic()
  drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

 drivers/gpu/drm/i915/display/intel_display.c | 316 +++++++++----------
 drivers/gpu/drm/i915/display/intel_fbc.c     |  14 +-
 drivers/gpu/drm/i915/display/intel_fbc.h     |   8 +-
 drivers/gpu/drm/i915/intel_pm.c              |   4 +-
 drivers/gpu/drm/i915/intel_pm.h              |   2 +-
 5 files changed, 154 insertions(+), 190 deletions(-)

-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/7] drm/i915: Clean up arguments to nv12/scaler w/a funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Don't pass the redundant dev_priv to needs_nv12_wa() and
needs_scalerclk_wa().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++---------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..d559b7ae1151 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6037,9 +6037,10 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	return !old_crtc_state->ips_enabled;
 }
 
-static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
-			  const struct intel_crtc_state *crtc_state)
+static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
 	if (!crtc_state->nv12_planes)
 		return false;
 
@@ -6050,9 +6051,10 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
 	return false;
 }
 
-static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
-			       const struct intel_crtc_state *crtc_state)
+static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
 	/* Wa_2006604312:icl */
 	if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
 		return true;
@@ -6093,12 +6095,12 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 			intel_post_enable_primary(&crtc->base, pipe_config);
 	}
 
-	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    !needs_nv12_wa(dev_priv, pipe_config))
+	if (needs_nv12_wa(old_crtc_state) &&
+	    !needs_nv12_wa(pipe_config))
 		skl_wa_827(dev_priv, crtc->pipe, false);
 
-	if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
-	    !needs_scalerclk_wa(dev_priv, pipe_config))
+	if (needs_scalerclk_wa(old_crtc_state) &&
+	    !needs_scalerclk_wa(pipe_config))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
@@ -6135,13 +6137,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	}
 
 	/* Display WA 827 */
-	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    needs_nv12_wa(dev_priv, pipe_config))
+	if (!needs_nv12_wa(old_crtc_state) &&
+	    needs_nv12_wa(pipe_config))
 		skl_wa_827(dev_priv, crtc->pipe, true);
 
 	/* Wa_2006604312:icl */
-	if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
-	    needs_scalerclk_wa(dev_priv, pipe_config))
+	if (!needs_scalerclk_wa(old_crtc_state) &&
+	    needs_scalerclk_wa(pipe_config))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
 
 	/*
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/7] drm/i915: Clean up arguments to nv12/scaler w/a funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Don't pass the redundant dev_priv to needs_nv12_wa() and
needs_scalerclk_wa().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++---------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..d559b7ae1151 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6037,9 +6037,10 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	return !old_crtc_state->ips_enabled;
 }
 
-static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
-			  const struct intel_crtc_state *crtc_state)
+static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
 	if (!crtc_state->nv12_planes)
 		return false;
 
@@ -6050,9 +6051,10 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
 	return false;
 }
 
-static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
-			       const struct intel_crtc_state *crtc_state)
+static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
 	/* Wa_2006604312:icl */
 	if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
 		return true;
@@ -6093,12 +6095,12 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 			intel_post_enable_primary(&crtc->base, pipe_config);
 	}
 
-	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    !needs_nv12_wa(dev_priv, pipe_config))
+	if (needs_nv12_wa(old_crtc_state) &&
+	    !needs_nv12_wa(pipe_config))
 		skl_wa_827(dev_priv, crtc->pipe, false);
 
-	if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
-	    !needs_scalerclk_wa(dev_priv, pipe_config))
+	if (needs_scalerclk_wa(old_crtc_state) &&
+	    !needs_scalerclk_wa(pipe_config))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
@@ -6135,13 +6137,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	}
 
 	/* Display WA 827 */
-	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    needs_nv12_wa(dev_priv, pipe_config))
+	if (!needs_nv12_wa(old_crtc_state) &&
+	    needs_nv12_wa(pipe_config))
 		skl_wa_827(dev_priv, crtc->pipe, true);
 
 	/* Wa_2006604312:icl */
-	if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
-	    needs_scalerclk_wa(dev_priv, pipe_config))
+	if (!needs_scalerclk_wa(old_crtc_state) &&
+	    needs_scalerclk_wa(pipe_config))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
 
 	/*
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/7] drm/i915: Clean up arguments to nv12/scaler w/a funcs

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Don't pass the redundant dev_priv to needs_nv12_wa() and
> needs_scalerclk_wa().
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++-------
> --
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 53dc310a5f6d..d559b7ae1151 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6037,9 +6037,10 @@ static bool hsw_post_update_enable_ips(const
> struct intel_crtc_state *old_crtc_s
>  	return !old_crtc_state->ips_enabled;
>  }
>  
> -static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> -			  const struct intel_crtc_state *crtc_state)
> +static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >uapi.crtc->dev);
> +
>  	if (!crtc_state->nv12_planes)
>  		return false;
>  
> @@ -6050,9 +6051,10 @@ static bool needs_nv12_wa(struct
> drm_i915_private *dev_priv,
>  	return false;
>  }
>  
> -static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
> -			       const struct intel_crtc_state
> *crtc_state)
> +static bool needs_scalerclk_wa(const struct intel_crtc_state
> *crtc_state)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >uapi.crtc->dev);
> +
>  	/* Wa_2006604312:icl */
>  	if (crtc_state->scaler_state.scaler_users > 0 &&
> IS_ICELAKE(dev_priv))
>  		return true;
> @@ -6093,12 +6095,12 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  			intel_post_enable_primary(&crtc->base,
> pipe_config);
>  	}
>  
> -	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    !needs_nv12_wa(dev_priv, pipe_config))
> +	if (needs_nv12_wa(old_crtc_state) &&
> +	    !needs_nv12_wa(pipe_config))
>  		skl_wa_827(dev_priv, crtc->pipe, false);
>  
> -	if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> -	    !needs_scalerclk_wa(dev_priv, pipe_config))
> +	if (needs_scalerclk_wa(old_crtc_state) &&
> +	    !needs_scalerclk_wa(pipe_config))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
> @@ -6135,13 +6137,13 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	}
>  
>  	/* Display WA 827 */
> -	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    needs_nv12_wa(dev_priv, pipe_config))
> +	if (!needs_nv12_wa(old_crtc_state) &&
> +	    needs_nv12_wa(pipe_config))
>  		skl_wa_827(dev_priv, crtc->pipe, true);
>  
>  	/* Wa_2006604312:icl */
> -	if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> -	    needs_scalerclk_wa(dev_priv, pipe_config))
> +	if (!needs_scalerclk_wa(old_crtc_state) &&
> +	    needs_scalerclk_wa(pipe_config))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
>  
>  	/*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Clean up arguments to nv12/scaler w/a funcs

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Don't pass the redundant dev_priv to needs_nv12_wa() and
> needs_scalerclk_wa().
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++-------
> --
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 53dc310a5f6d..d559b7ae1151 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6037,9 +6037,10 @@ static bool hsw_post_update_enable_ips(const
> struct intel_crtc_state *old_crtc_s
>  	return !old_crtc_state->ips_enabled;
>  }
>  
> -static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> -			  const struct intel_crtc_state *crtc_state)
> +static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >uapi.crtc->dev);
> +
>  	if (!crtc_state->nv12_planes)
>  		return false;
>  
> @@ -6050,9 +6051,10 @@ static bool needs_nv12_wa(struct
> drm_i915_private *dev_priv,
>  	return false;
>  }
>  
> -static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
> -			       const struct intel_crtc_state
> *crtc_state)
> +static bool needs_scalerclk_wa(const struct intel_crtc_state
> *crtc_state)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >uapi.crtc->dev);
> +
>  	/* Wa_2006604312:icl */
>  	if (crtc_state->scaler_state.scaler_users > 0 &&
> IS_ICELAKE(dev_priv))
>  		return true;
> @@ -6093,12 +6095,12 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  			intel_post_enable_primary(&crtc->base,
> pipe_config);
>  	}
>  
> -	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    !needs_nv12_wa(dev_priv, pipe_config))
> +	if (needs_nv12_wa(old_crtc_state) &&
> +	    !needs_nv12_wa(pipe_config))
>  		skl_wa_827(dev_priv, crtc->pipe, false);
>  
> -	if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> -	    !needs_scalerclk_wa(dev_priv, pipe_config))
> +	if (needs_scalerclk_wa(old_crtc_state) &&
> +	    !needs_scalerclk_wa(pipe_config))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
> @@ -6135,13 +6137,13 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	}
>  
>  	/* Display WA 827 */
> -	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> -	    needs_nv12_wa(dev_priv, pipe_config))
> +	if (!needs_nv12_wa(old_crtc_state) &&
> +	    needs_nv12_wa(pipe_config))
>  		skl_wa_827(dev_priv, crtc->pipe, true);
>  
>  	/* Wa_2006604312:icl */
> -	if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> -	    needs_scalerclk_wa(dev_priv, pipe_config))
> +	if (!needs_scalerclk_wa(old_crtc_state) &&
> +	    needs_scalerclk_wa(pipe_config))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
>  
>  	/*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/7] drm/i915: Pass dev_priv to ilk_disable_lp_wm()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of another 'dev' usage by passing dev_priv instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_pm.c              | 4 +---
 drivers/gpu/drm/i915/intel_pm.h              | 2 +-
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d559b7ae1151..89c8f818f289 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6166,7 +6166,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 *
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
-	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
+	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv) &&
 	    old_crtc_state->hw.active)
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..8d63672452a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3592,10 +3592,8 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	dev_priv->wm.hw = *results;
 }
 
-bool ilk_disable_lp_wm(struct drm_device *dev)
+bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
-
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..c06c6a846d9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -54,7 +54,7 @@ void skl_write_plane_wm(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state);
 void skl_write_cursor_wm(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state);
-bool ilk_disable_lp_wm(struct drm_device *dev);
+bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
 void intel_init_ipc(struct drm_i915_private *dev_priv);
 void intel_enable_ipc(struct drm_i915_private *dev_priv);
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/7] drm/i915: Pass dev_priv to ilk_disable_lp_wm()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of another 'dev' usage by passing dev_priv instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_pm.c              | 4 +---
 drivers/gpu/drm/i915/intel_pm.h              | 2 +-
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d559b7ae1151..89c8f818f289 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6166,7 +6166,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 *
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
-	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
+	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv) &&
 	    old_crtc_state->hw.active)
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..8d63672452a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3592,10 +3592,8 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	dev_priv->wm.hw = *results;
 }
 
-bool ilk_disable_lp_wm(struct drm_device *dev)
+bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
-
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..c06c6a846d9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -54,7 +54,7 @@ void skl_write_plane_wm(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state);
 void skl_write_cursor_wm(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state);
-bool ilk_disable_lp_wm(struct drm_device *dev);
+bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
 void intel_init_ipc(struct drm_i915_private *dev_priv);
 void intel_enable_ipc(struct drm_i915_private *dev_priv);
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/7] drm/i915: Pass dev_priv to ilk_disable_lp_wm()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Get rid of another 'dev' usage by passing dev_priv instead.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c              | 4 +---
>  drivers/gpu/drm/i915/intel_pm.h              | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d559b7ae1151..89c8f818f289 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6166,7 +6166,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 *
>  	 * WaCxSRDisabledForSpriteScaling:ivb
>  	 */
> -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
> +	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> &&
>  	    old_crtc_state->hw.active)
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 5aad9d49a528..8d63672452a9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3592,10 +3592,8 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
>  	dev_priv->wm.hw = *results;
>  }
>  
> -bool ilk_disable_lp_wm(struct drm_device *dev)
> +bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -
>  	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.h
> b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..c06c6a846d9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -54,7 +54,7 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state);
>  void skl_write_cursor_wm(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state);
> -bool ilk_disable_lp_wm(struct drm_device *dev);
> +bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
>  void intel_init_ipc(struct drm_i915_private *dev_priv);
>  void intel_enable_ipc(struct drm_i915_private *dev_priv);
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Pass dev_priv to ilk_disable_lp_wm()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Get rid of another 'dev' usage by passing dev_priv instead.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c              | 4 +---
>  drivers/gpu/drm/i915/intel_pm.h              | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d559b7ae1151..89c8f818f289 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6166,7 +6166,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 *
>  	 * WaCxSRDisabledForSpriteScaling:ivb
>  	 */
> -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
> +	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> &&
>  	    old_crtc_state->hw.active)
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 5aad9d49a528..8d63672452a9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3592,10 +3592,8 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
>  	dev_priv->wm.hw = *results;
>  }
>  
> -bool ilk_disable_lp_wm(struct drm_device *dev)
> +bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -
>  	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.h
> b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..c06c6a846d9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -54,7 +54,7 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state);
>  void skl_write_cursor_wm(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state);
> -bool ilk_disable_lp_wm(struct drm_device *dev);
> +bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
>  void intel_init_ipc(struct drm_i915_private *dev_priv);
>  void intel_enable_ipc(struct drm_i915_private *dev_priv);
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the old world 'pipe_config' variable name with the new thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++----------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89c8f818f289..e341b97b7dec 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
 						crtc);
 	struct drm_plane *primary = crtc->base.primary;
 	struct drm_plane_state *old_primary_state =
 		drm_atomic_get_old_plane_state(state, primary);
 
-	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
+	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state->fb_bits);
 
-	if (pipe_config->update_wm_post && pipe_config->hw.active)
+	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(crtc);
 
-	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
-		hsw_enable_ips(pipe_config);
+	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
+		hsw_enable_ips(new_crtc_state);
 
 	if (old_primary_state) {
 		struct drm_plane_state *new_primary_state =
@@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 		intel_fbc_post_update(crtc);
 
 		if (new_primary_state->visible &&
-		    (needs_modeset(pipe_config) ||
+		    (needs_modeset(new_crtc_state) ||
 		     !old_primary_state->visible))
-			intel_post_enable_primary(&crtc->base, pipe_config);
+			intel_post_enable_primary(&crtc->base, new_crtc_state);
 	}
 
 	if (needs_nv12_wa(old_crtc_state) &&
-	    !needs_nv12_wa(pipe_config))
+	    !needs_nv12_wa(new_crtc_state))
 		skl_wa_827(dev_priv, crtc->pipe, false);
 
 	if (needs_scalerclk_wa(old_crtc_state) &&
-	    !needs_scalerclk_wa(pipe_config))
+	    !needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
-				   struct intel_crtc_state *pipe_config)
+				   struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
@@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	struct drm_plane *primary = crtc->base.primary;
 	struct drm_plane_state *old_primary_state =
 		drm_atomic_get_old_plane_state(state, primary);
-	bool modeset = needs_modeset(pipe_config);
+	bool modeset = needs_modeset(new_crtc_state);
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(state);
 
-	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
+	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
 	if (old_primary_state) {
@@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 			intel_atomic_get_new_plane_state(intel_state,
 							 to_intel_plane(primary));
 
-		intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
+		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
 		/*
 		 * Gen2 reports pipe underruns whenever all planes are disabled.
 		 * So disable underrun reporting before all the planes get disabled.
@@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 
 	/* Display WA 827 */
 	if (!needs_nv12_wa(old_crtc_state) &&
-	    needs_nv12_wa(pipe_config))
+	    needs_nv12_wa(new_crtc_state))
 		skl_wa_827(dev_priv, crtc->pipe, true);
 
 	/* Wa_2006604312:icl */
 	if (!needs_scalerclk_wa(old_crtc_state) &&
-	    needs_scalerclk_wa(pipe_config))
+	    needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
 
 	/*
@@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * wait-for-vblank between disabling the plane and the pipe.
 	 */
 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
-	    pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
+	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
 	/*
@@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 *
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
-	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv) &&
-	    old_crtc_state->hw.active)
+	if (old_crtc_state->hw.active &&
+	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
 	/*
 	 * If we're doing a modeset, we're done.  No need to do any pre-vblank
 	 * watermark programming here.
 	 */
-	if (needs_modeset(pipe_config))
+	if (needs_modeset(new_crtc_state))
 		return;
 
 	/*
@@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 */
 	if (dev_priv->display.initial_watermarks)
 		dev_priv->display.initial_watermarks(intel_state, crtc);
-	else if (pipe_config->update_wm_pre)
+	else if (new_crtc_state->update_wm_pre)
 		intel_update_watermarks(crtc);
 }
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the old world 'pipe_config' variable name with the new thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++----------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89c8f818f289..e341b97b7dec 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
 						crtc);
 	struct drm_plane *primary = crtc->base.primary;
 	struct drm_plane_state *old_primary_state =
 		drm_atomic_get_old_plane_state(state, primary);
 
-	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
+	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state->fb_bits);
 
-	if (pipe_config->update_wm_post && pipe_config->hw.active)
+	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(crtc);
 
-	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
-		hsw_enable_ips(pipe_config);
+	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
+		hsw_enable_ips(new_crtc_state);
 
 	if (old_primary_state) {
 		struct drm_plane_state *new_primary_state =
@@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 		intel_fbc_post_update(crtc);
 
 		if (new_primary_state->visible &&
-		    (needs_modeset(pipe_config) ||
+		    (needs_modeset(new_crtc_state) ||
 		     !old_primary_state->visible))
-			intel_post_enable_primary(&crtc->base, pipe_config);
+			intel_post_enable_primary(&crtc->base, new_crtc_state);
 	}
 
 	if (needs_nv12_wa(old_crtc_state) &&
-	    !needs_nv12_wa(pipe_config))
+	    !needs_nv12_wa(new_crtc_state))
 		skl_wa_827(dev_priv, crtc->pipe, false);
 
 	if (needs_scalerclk_wa(old_crtc_state) &&
-	    !needs_scalerclk_wa(pipe_config))
+	    !needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
-				   struct intel_crtc_state *pipe_config)
+				   struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
@@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	struct drm_plane *primary = crtc->base.primary;
 	struct drm_plane_state *old_primary_state =
 		drm_atomic_get_old_plane_state(state, primary);
-	bool modeset = needs_modeset(pipe_config);
+	bool modeset = needs_modeset(new_crtc_state);
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(state);
 
-	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
+	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
 	if (old_primary_state) {
@@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 			intel_atomic_get_new_plane_state(intel_state,
 							 to_intel_plane(primary));
 
-		intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
+		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
 		/*
 		 * Gen2 reports pipe underruns whenever all planes are disabled.
 		 * So disable underrun reporting before all the planes get disabled.
@@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 
 	/* Display WA 827 */
 	if (!needs_nv12_wa(old_crtc_state) &&
-	    needs_nv12_wa(pipe_config))
+	    needs_nv12_wa(new_crtc_state))
 		skl_wa_827(dev_priv, crtc->pipe, true);
 
 	/* Wa_2006604312:icl */
 	if (!needs_scalerclk_wa(old_crtc_state) &&
-	    needs_scalerclk_wa(pipe_config))
+	    needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
 
 	/*
@@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * wait-for-vblank between disabling the plane and the pipe.
 	 */
 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
-	    pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
+	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
 	/*
@@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 *
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
-	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv) &&
-	    old_crtc_state->hw.active)
+	if (old_crtc_state->hw.active &&
+	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
 	/*
 	 * If we're doing a modeset, we're done.  No need to do any pre-vblank
 	 * watermark programming here.
 	 */
-	if (needs_modeset(pipe_config))
+	if (needs_modeset(new_crtc_state))
 		return;
 
 	/*
@@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 */
 	if (dev_priv->display.initial_watermarks)
 		dev_priv->display.initial_watermarks(intel_state, crtc);
-	else if (pipe_config->update_wm_pre)
+	else if (new_crtc_state->update_wm_pre)
 		intel_update_watermarks(crtc);
 }
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the old world 'pipe_config' variable name with the new thing.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++------
> ----
>  1 file changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 89c8f818f289..e341b97b7dec 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct intel_crtc_state *pipe_config =
> +	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> tate),
>  						crtc);
>  	struct drm_plane *primary = crtc->base.primary;
>  	struct drm_plane_state *old_primary_state =
>  		drm_atomic_get_old_plane_state(state, primary);
>  
> -	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config-
> >fb_bits);
> +	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> >fb_bits);
>  
> -	if (pipe_config->update_wm_post && pipe_config->hw.active)
> +	if (new_crtc_state->update_wm_post && new_crtc_state-
> >hw.active)
>  		intel_update_watermarks(crtc);
>  
> -	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> -		hsw_enable_ips(pipe_config);
> +	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> +		hsw_enable_ips(new_crtc_state);
>  
>  	if (old_primary_state) {
>  		struct drm_plane_state *new_primary_state =
> @@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  		intel_fbc_post_update(crtc);
>  
>  		if (new_primary_state->visible &&
> -		    (needs_modeset(pipe_config) ||
> +		    (needs_modeset(new_crtc_state) ||
>  		     !old_primary_state->visible))
> -			intel_post_enable_primary(&crtc->base,
> pipe_config);
> +			intel_post_enable_primary(&crtc->base,
> new_crtc_state);
>  	}
>  
>  	if (needs_nv12_wa(old_crtc_state) &&
> -	    !needs_nv12_wa(pipe_config))
> +	    !needs_nv12_wa(new_crtc_state))
>  		skl_wa_827(dev_priv, crtc->pipe, false);
>  
>  	if (needs_scalerclk_wa(old_crtc_state) &&
> -	    !needs_scalerclk_wa(pipe_config))
> +	    !needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_crtc_state
> *old_crtc_state,
> -				   struct intel_crtc_state
> *pipe_config)
> +				   struct intel_crtc_state
> *new_crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
> @@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	struct drm_plane *primary = crtc->base.primary;
>  	struct drm_plane_state *old_primary_state =
>  		drm_atomic_get_old_plane_state(state, primary);
> -	bool modeset = needs_modeset(pipe_config);
> +	bool modeset = needs_modeset(new_crtc_state);
>  	struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(state);
>  
> -	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
> +	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
>  	if (old_primary_state) {
> @@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  			intel_atomic_get_new_plane_state(intel_state,
>  							 to_intel_plane
> (primary));
>  
> -		intel_fbc_pre_update(crtc, pipe_config,
> new_primary_state);
> +		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
>  		/*
>  		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
>  		 * So disable underrun reporting before all the planes
> get disabled.
> @@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  
>  	/* Display WA 827 */
>  	if (!needs_nv12_wa(old_crtc_state) &&
> -	    needs_nv12_wa(pipe_config))
> +	    needs_nv12_wa(new_crtc_state))
>  		skl_wa_827(dev_priv, crtc->pipe, true);
>  
>  	/* Wa_2006604312:icl */
>  	if (!needs_scalerclk_wa(old_crtc_state) &&
> -	    needs_scalerclk_wa(pipe_config))
> +	    needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
>  
>  	/*
> @@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 * wait-for-vblank between disabling the plane and the pipe.
>  	 */
>  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> -	    pipe_config->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
> +	    new_crtc_state->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
>  	/*
> @@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 *
>  	 * WaCxSRDisabledForSpriteScaling:ivb
>  	 */
> -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> &&
> -	    old_crtc_state->hw.active)
> +	if (old_crtc_state->hw.active &&
> +	    new_crtc_state->disable_lp_wm &&
> ilk_disable_lp_wm(dev_priv))
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
>  	/*
>  	 * If we're doing a modeset, we're done.  No need to do any
> pre-vblank
>  	 * watermark programming here.
>  	 */
> -	if (needs_modeset(pipe_config))
> +	if (needs_modeset(new_crtc_state))
>  		return;
>  
>  	/*
> @@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 */
>  	if (dev_priv->display.initial_watermarks)
>  		dev_priv->display.initial_watermarks(intel_state,
> crtc);
> -	else if (pipe_config->update_wm_pre)
> +	else if (new_crtc_state->update_wm_pre)
>  		intel_update_watermarks(crtc);
>  }
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the old world 'pipe_config' variable name with the new thing.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++------
> ----
>  1 file changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 89c8f818f289..e341b97b7dec 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct intel_crtc_state *pipe_config =
> +	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> tate),
>  						crtc);
>  	struct drm_plane *primary = crtc->base.primary;
>  	struct drm_plane_state *old_primary_state =
>  		drm_atomic_get_old_plane_state(state, primary);
>  
> -	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config-
> >fb_bits);
> +	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> >fb_bits);
>  
> -	if (pipe_config->update_wm_post && pipe_config->hw.active)
> +	if (new_crtc_state->update_wm_post && new_crtc_state-
> >hw.active)
>  		intel_update_watermarks(crtc);
>  
> -	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> -		hsw_enable_ips(pipe_config);
> +	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> +		hsw_enable_ips(new_crtc_state);
>  
>  	if (old_primary_state) {
>  		struct drm_plane_state *new_primary_state =
> @@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  		intel_fbc_post_update(crtc);
>  
>  		if (new_primary_state->visible &&
> -		    (needs_modeset(pipe_config) ||
> +		    (needs_modeset(new_crtc_state) ||
>  		     !old_primary_state->visible))
> -			intel_post_enable_primary(&crtc->base,
> pipe_config);
> +			intel_post_enable_primary(&crtc->base,
> new_crtc_state);
>  	}
>  
>  	if (needs_nv12_wa(old_crtc_state) &&
> -	    !needs_nv12_wa(pipe_config))
> +	    !needs_nv12_wa(new_crtc_state))
>  		skl_wa_827(dev_priv, crtc->pipe, false);
>  
>  	if (needs_scalerclk_wa(old_crtc_state) &&
> -	    !needs_scalerclk_wa(pipe_config))
> +	    !needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_crtc_state
> *old_crtc_state,
> -				   struct intel_crtc_state
> *pipe_config)
> +				   struct intel_crtc_state
> *new_crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
> @@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	struct drm_plane *primary = crtc->base.primary;
>  	struct drm_plane_state *old_primary_state =
>  		drm_atomic_get_old_plane_state(state, primary);
> -	bool modeset = needs_modeset(pipe_config);
> +	bool modeset = needs_modeset(new_crtc_state);
>  	struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(state);
>  
> -	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
> +	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
>  	if (old_primary_state) {
> @@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  			intel_atomic_get_new_plane_state(intel_state,
>  							 to_intel_plane
> (primary));
>  
> -		intel_fbc_pre_update(crtc, pipe_config,
> new_primary_state);
> +		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
>  		/*
>  		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
>  		 * So disable underrun reporting before all the planes
> get disabled.
> @@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  
>  	/* Display WA 827 */
>  	if (!needs_nv12_wa(old_crtc_state) &&
> -	    needs_nv12_wa(pipe_config))
> +	    needs_nv12_wa(new_crtc_state))
>  		skl_wa_827(dev_priv, crtc->pipe, true);
>  
>  	/* Wa_2006604312:icl */
>  	if (!needs_scalerclk_wa(old_crtc_state) &&
> -	    needs_scalerclk_wa(pipe_config))
> +	    needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
>  
>  	/*
> @@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 * wait-for-vblank between disabling the plane and the pipe.
>  	 */
>  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> -	    pipe_config->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
> +	    new_crtc_state->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
>  	/*
> @@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 *
>  	 * WaCxSRDisabledForSpriteScaling:ivb
>  	 */
> -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> &&
> -	    old_crtc_state->hw.active)
> +	if (old_crtc_state->hw.active &&
> +	    new_crtc_state->disable_lp_wm &&
> ilk_disable_lp_wm(dev_priv))
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
>  	/*
>  	 * If we're doing a modeset, we're done.  No need to do any
> pre-vblank
>  	 * watermark programming here.
>  	 */
> -	if (needs_modeset(pipe_config))
> +	if (needs_modeset(new_crtc_state))
>  		return;
>  
>  	/*
> @@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 */
>  	if (dev_priv->display.initial_watermarks)
>  		dev_priv->display.initial_watermarks(intel_state,
> crtc);
> -	else if (pipe_config->update_wm_pre)
> +	else if (new_crtc_state->update_wm_pre)
>  		intel_update_watermarks(crtc);
>  }
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 23:09 +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Replace the old world 'pipe_config' variable name with the new
> > thing.
> > 

I guess you mean old word 'pipe_config'?

> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++------
> > ----
> >  1 file changed, 20 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 89c8f818f289..e341b97b7dec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct intel_crtc_state *pipe_config =
> > +	struct intel_crtc_state *new_crtc_state =
> >  		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > tate),
> >  						crtc);
> >  	struct drm_plane *primary = crtc->base.primary;
> >  	struct drm_plane_state *old_primary_state =
> >  		drm_atomic_get_old_plane_state(state, primary);
> >  
> > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config-
> > > fb_bits);
> > +	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > > fb_bits);
> >  
> > -	if (pipe_config->update_wm_post && pipe_config->hw.active)
> > +	if (new_crtc_state->update_wm_post && new_crtc_state-
> > > hw.active)
> >  		intel_update_watermarks(crtc);
> >  
> > -	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> > -		hsw_enable_ips(pipe_config);
> > +	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> > +		hsw_enable_ips(new_crtc_state);
> >  
> >  	if (old_primary_state) {
> >  		struct drm_plane_state *new_primary_state =
> > @@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  		intel_fbc_post_update(crtc);
> >  
> >  		if (new_primary_state->visible &&
> > -		    (needs_modeset(pipe_config) ||
> > +		    (needs_modeset(new_crtc_state) ||
> >  		     !old_primary_state->visible))
> > -			intel_post_enable_primary(&crtc->base,
> > pipe_config);
> > +			intel_post_enable_primary(&crtc->base,
> > new_crtc_state);
> >  	}
> >  
> >  	if (needs_nv12_wa(old_crtc_state) &&
> > -	    !needs_nv12_wa(pipe_config))
> > +	    !needs_nv12_wa(new_crtc_state))
> >  		skl_wa_827(dev_priv, crtc->pipe, false);
> >  
> >  	if (needs_scalerclk_wa(old_crtc_state) &&
> > -	    !needs_scalerclk_wa(pipe_config))
> > +	    !needs_scalerclk_wa(new_crtc_state))
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> >  }
> >  
> >  static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > -				   struct intel_crtc_state
> > *pipe_config)
> > +				   struct intel_crtc_state
> > *new_crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > uapi.crtc);
> >  	struct drm_device *dev = crtc->base.dev;
> > @@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	struct drm_plane *primary = crtc->base.primary;
> >  	struct drm_plane_state *old_primary_state =
> >  		drm_atomic_get_old_plane_state(state, primary);
> > -	bool modeset = needs_modeset(pipe_config);
> > +	bool modeset = needs_modeset(new_crtc_state);
> >  	struct intel_atomic_state *intel_state =
> >  		to_intel_atomic_state(state);
> >  
> > -	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
> > +	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_disable_ips(old_crtc_state);
> >  
> >  	if (old_primary_state) {
> > @@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  			intel_atomic_get_new_plane_state(intel_state,
> >  							 to_intel_plane
> > (primary));
> >  
> > -		intel_fbc_pre_update(crtc, pipe_config,
> > new_primary_state);
> > +		intel_fbc_pre_update(crtc, new_crtc_state,
> > new_primary_state);
> >  		/*
> >  		 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> >  		 * So disable underrun reporting before all the planes
> > get disabled.
> > @@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  
> >  	/* Display WA 827 */
> >  	if (!needs_nv12_wa(old_crtc_state) &&
> > -	    needs_nv12_wa(pipe_config))
> > +	    needs_nv12_wa(new_crtc_state))
> >  		skl_wa_827(dev_priv, crtc->pipe, true);
> >  
> >  	/* Wa_2006604312:icl */
> >  	if (!needs_scalerclk_wa(old_crtc_state) &&
> > -	    needs_scalerclk_wa(pipe_config))
> > +	    needs_scalerclk_wa(new_crtc_state))
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> >  
> >  	/*
> > @@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 * wait-for-vblank between disabling the plane and the pipe.
> >  	 */
> >  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> > -	    pipe_config->disable_cxsr &&
> > intel_set_memory_cxsr(dev_priv, false))
> > +	    new_crtc_state->disable_cxsr &&
> > intel_set_memory_cxsr(dev_priv, false))
> >  		intel_wait_for_vblank(dev_priv, crtc->pipe);
> >  
> >  	/*
> > @@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 *
> >  	 * WaCxSRDisabledForSpriteScaling:ivb
> >  	 */
> > -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> > &&
> > -	    old_crtc_state->hw.active)
> > +	if (old_crtc_state->hw.active &&
> > +	    new_crtc_state->disable_lp_wm &&
> > ilk_disable_lp_wm(dev_priv))
> >  		intel_wait_for_vblank(dev_priv, crtc->pipe);
> >  
> >  	/*
> >  	 * If we're doing a modeset, we're done.  No need to do any
> > pre-vblank
> >  	 * watermark programming here.
> >  	 */
> > -	if (needs_modeset(pipe_config))
> > +	if (needs_modeset(new_crtc_state))
> >  		return;
> >  
> >  	/*
> > @@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 */
> >  	if (dev_priv->display.initial_watermarks)
> >  		dev_priv->display.initial_watermarks(intel_state,
> > crtc);
> > -	else if (pipe_config->update_wm_pre)
> > +	else if (new_crtc_state->update_wm_pre)
> >  		intel_update_watermarks(crtc);
> >  }
> >  
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 23:09 +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Replace the old world 'pipe_config' variable name with the new
> > thing.
> > 

I guess you mean old word 'pipe_config'?

> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++------
> > ----
> >  1 file changed, 20 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 89c8f818f289..e341b97b7dec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6068,20 +6068,20 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct intel_crtc_state *pipe_config =
> > +	struct intel_crtc_state *new_crtc_state =
> >  		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > tate),
> >  						crtc);
> >  	struct drm_plane *primary = crtc->base.primary;
> >  	struct drm_plane_state *old_primary_state =
> >  		drm_atomic_get_old_plane_state(state, primary);
> >  
> > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config-
> > > fb_bits);
> > +	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > > fb_bits);
> >  
> > -	if (pipe_config->update_wm_post && pipe_config->hw.active)
> > +	if (new_crtc_state->update_wm_post && new_crtc_state-
> > > hw.active)
> >  		intel_update_watermarks(crtc);
> >  
> > -	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> > -		hsw_enable_ips(pipe_config);
> > +	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> > +		hsw_enable_ips(new_crtc_state);
> >  
> >  	if (old_primary_state) {
> >  		struct drm_plane_state *new_primary_state =
> > @@ -6090,22 +6090,22 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  		intel_fbc_post_update(crtc);
> >  
> >  		if (new_primary_state->visible &&
> > -		    (needs_modeset(pipe_config) ||
> > +		    (needs_modeset(new_crtc_state) ||
> >  		     !old_primary_state->visible))
> > -			intel_post_enable_primary(&crtc->base,
> > pipe_config);
> > +			intel_post_enable_primary(&crtc->base,
> > new_crtc_state);
> >  	}
> >  
> >  	if (needs_nv12_wa(old_crtc_state) &&
> > -	    !needs_nv12_wa(pipe_config))
> > +	    !needs_nv12_wa(new_crtc_state))
> >  		skl_wa_827(dev_priv, crtc->pipe, false);
> >  
> >  	if (needs_scalerclk_wa(old_crtc_state) &&
> > -	    !needs_scalerclk_wa(pipe_config))
> > +	    !needs_scalerclk_wa(new_crtc_state))
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> >  }
> >  
> >  static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > -				   struct intel_crtc_state
> > *pipe_config)
> > +				   struct intel_crtc_state
> > *new_crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > uapi.crtc);
> >  	struct drm_device *dev = crtc->base.dev;
> > @@ -6114,11 +6114,11 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	struct drm_plane *primary = crtc->base.primary;
> >  	struct drm_plane_state *old_primary_state =
> >  		drm_atomic_get_old_plane_state(state, primary);
> > -	bool modeset = needs_modeset(pipe_config);
> > +	bool modeset = needs_modeset(new_crtc_state);
> >  	struct intel_atomic_state *intel_state =
> >  		to_intel_atomic_state(state);
> >  
> > -	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
> > +	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_disable_ips(old_crtc_state);
> >  
> >  	if (old_primary_state) {
> > @@ -6126,7 +6126,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  			intel_atomic_get_new_plane_state(intel_state,
> >  							 to_intel_plane
> > (primary));
> >  
> > -		intel_fbc_pre_update(crtc, pipe_config,
> > new_primary_state);
> > +		intel_fbc_pre_update(crtc, new_crtc_state,
> > new_primary_state);
> >  		/*
> >  		 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> >  		 * So disable underrun reporting before all the planes
> > get disabled.
> > @@ -6138,12 +6138,12 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  
> >  	/* Display WA 827 */
> >  	if (!needs_nv12_wa(old_crtc_state) &&
> > -	    needs_nv12_wa(pipe_config))
> > +	    needs_nv12_wa(new_crtc_state))
> >  		skl_wa_827(dev_priv, crtc->pipe, true);
> >  
> >  	/* Wa_2006604312:icl */
> >  	if (!needs_scalerclk_wa(old_crtc_state) &&
> > -	    needs_scalerclk_wa(pipe_config))
> > +	    needs_scalerclk_wa(new_crtc_state))
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> >  
> >  	/*
> > @@ -6156,7 +6156,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 * wait-for-vblank between disabling the plane and the pipe.
> >  	 */
> >  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> > -	    pipe_config->disable_cxsr &&
> > intel_set_memory_cxsr(dev_priv, false))
> > +	    new_crtc_state->disable_cxsr &&
> > intel_set_memory_cxsr(dev_priv, false))
> >  		intel_wait_for_vblank(dev_priv, crtc->pipe);
> >  
> >  	/*
> > @@ -6166,15 +6166,15 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 *
> >  	 * WaCxSRDisabledForSpriteScaling:ivb
> >  	 */
> > -	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev_priv)
> > &&
> > -	    old_crtc_state->hw.active)
> > +	if (old_crtc_state->hw.active &&
> > +	    new_crtc_state->disable_lp_wm &&
> > ilk_disable_lp_wm(dev_priv))
> >  		intel_wait_for_vblank(dev_priv, crtc->pipe);
> >  
> >  	/*
> >  	 * If we're doing a modeset, we're done.  No need to do any
> > pre-vblank
> >  	 * watermark programming here.
> >  	 */
> > -	if (needs_modeset(pipe_config))
> > +	if (needs_modeset(new_crtc_state))
> >  		return;
> >  
> >  	/*
> > @@ -6193,7 +6193,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 */
> >  	if (dev_priv->display.initial_watermarks)
> >  		dev_priv->display.initial_watermarks(intel_state,
> > crtc);
> > -	else if (pipe_config->update_wm_pre)
> > +	else if (new_crtc_state->update_wm_pre)
> >  		intel_update_watermarks(crtc);
> >  }
> >  
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Ville Syrjälä]

On Wed, Nov 27, 2019 at 11:11:15PM +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 23:09 +0000, Souza, Jose wrote:
> > On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Replace the old world 'pipe_config' variable name with the new
> > > thing.
> > > 
> 
> I guess you mean old word 'pipe_config'?

No.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/7] drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()

[Ville Syrjälä]

On Wed, Nov 27, 2019 at 11:11:15PM +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 23:09 +0000, Souza, Jose wrote:
> > On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Replace the old world 'pipe_config' variable name with the new
> > > thing.
> > > 
> 
> I guess you mean old word 'pipe_config'?

No.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Change the calling convention to just pass the state+crtc and
switch to intel_ types throughout.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++-----------
 drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
 drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
 3 files changed, 51 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e341b97b7dec..72655b5b1365 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5920,13 +5920,10 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
  * completely hide the primary plane.
  */
 static void
-intel_post_enable_primary(struct drm_crtc *crtc,
-			  const struct intel_crtc_state *new_crtc_state)
+intel_post_enable_primary(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	/*
 	 * Gen2 reports pipe underruns whenever all planes are disabled.
@@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
-static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
+static void intel_post_plane_update(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
-						crtc);
-	struct drm_plane *primary = crtc->base.primary;
-	struct drm_plane_state *old_primary_state =
-		drm_atomic_get_old_plane_state(state, primary);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_plane_state *old_primary_state =
+		intel_atomic_get_old_plane_state(state, primary);
+	const struct intel_plane_state *new_primary_state =
+		intel_atomic_get_new_plane_state(state, primary);
 
-	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state->fb_bits);
+	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 
 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(crtc);
@@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
 
-	if (old_primary_state) {
-		struct drm_plane_state *new_primary_state =
-			drm_atomic_get_new_plane_state(state, primary);
-
+	if (new_primary_state) {
 		intel_fbc_post_update(crtc);
 
-		if (new_primary_state->visible &&
+		if (new_primary_state->uapi.visible &&
 		    (needs_modeset(new_crtc_state) ||
-		     !old_primary_state->visible))
-			intel_post_enable_primary(&crtc->base, new_crtc_state);
+		     !old_primary_state->uapi.visible))
+			intel_post_enable_primary(crtc);
 	}
 
 	if (needs_nv12_wa(old_crtc_state) &&
@@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
-static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
-				   struct intel_crtc_state *new_crtc_state)
+static void intel_pre_plane_update(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct drm_plane *primary = crtc->base.primary;
-	struct drm_plane_state *old_primary_state =
-		drm_atomic_get_old_plane_state(state, primary);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_plane_state *old_primary_state =
+		intel_atomic_get_old_plane_state(state, primary);
+	const struct intel_plane_state *new_primary_state =
+		intel_atomic_get_new_plane_state(state, primary);
 	bool modeset = needs_modeset(new_crtc_state);
-	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(state);
 
 	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
-	if (old_primary_state) {
-		struct intel_plane_state *new_primary_state =
-			intel_atomic_get_new_plane_state(intel_state,
-							 to_intel_plane(primary));
-
+	if (new_primary_state) {
 		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
 		/*
 		 * Gen2 reports pipe underruns whenever all planes are disabled.
 		 * So disable underrun reporting before all the planes get disabled.
 		 */
-		if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
+		if (IS_GEN(dev_priv, 2) && old_primary_state->uapi.visible &&
 		    (modeset || !new_primary_state->uapi.visible))
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 	}
@@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * us to.
 	 */
 	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(intel_state, crtc);
+		dev_priv->display.initial_watermarks(state, crtc);
 	else if (new_crtc_state->update_wm_pre)
 		intel_update_watermarks(crtc);
 }
@@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
 		     new_crtc_state->update_pipe))
 			intel_color_load_luts(new_crtc_state);
 
-		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_pre_plane_update(state, crtc);
 
 		if (new_crtc_state->update_pipe)
 			intel_encoders_update_pipe(state, crtc);
@@ -14460,7 +14452,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
 		!old_slave_crtc_state);
 
 	/* Disable Slave first */
-	intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+	intel_pre_plane_update(state, slave_crtc);
 	if (old_slave_crtc_state->hw.active)
 		intel_old_crtc_state_disables(state,
 					      old_slave_crtc_state,
@@ -14468,7 +14460,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
 					      slave_crtc);
 
 	/* Disable Master */
-	intel_pre_plane_update(old_crtc_state, new_crtc_state);
+	intel_pre_plane_update(state, crtc);
 	if (old_crtc_state->hw.active)
 		intel_old_crtc_state_disables(state,
 					      old_crtc_state,
@@ -14508,7 +14500,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 			else
 				continue;
 		} else {
-			intel_pre_plane_update(old_crtc_state, new_crtc_state);
+			intel_pre_plane_update(state, crtc);
 
 			if (old_crtc_state->hw.active)
 				intel_old_crtc_state_disables(state,
@@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-		intel_post_plane_update(old_crtc_state);
+		intel_post_plane_update(state, crtc);
 
 		if (put_domains[i])
 			modeset_put_power_domains(dev_priv, put_domains[i]);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 92c7eb243559..70c56abe1a83 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 }
 
 static bool multiple_pipes_ok(struct intel_crtc *crtc,
-			      struct intel_plane_state *plane_state)
+			      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -656,8 +656,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 }
 
 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
-					 struct intel_crtc_state *crtc_state,
-					 struct intel_plane_state *plane_state)
+					 const struct intel_crtc_state *crtc_state,
+					 const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 }
 
 void intel_fbc_pre_update(struct intel_crtc *crtc,
-			  struct intel_crtc_state *crtc_state,
-			  struct intel_plane_state *plane_state)
+			  const struct intel_crtc_state *crtc_state,
+			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
  * intel_fbc_disable in the middle, as long as it is deactivated.
  */
 void intel_fbc_enable(struct intel_crtc *crtc,
-		      struct intel_crtc_state *crtc_state,
-		      struct intel_plane_state *plane_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 50272eda8d43..f58b0b1e3c5c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 			   struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
 void intel_fbc_pre_update(struct intel_crtc *crtc,
-			  struct intel_crtc_state *crtc_state,
-			  struct intel_plane_state *plane_state);
+			  const struct intel_crtc_state *crtc_state,
+			  const struct intel_plane_state *plane_state);
 void intel_fbc_post_update(struct intel_crtc *crtc);
 void intel_fbc_init(struct drm_i915_private *dev_priv);
 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
 void intel_fbc_enable(struct intel_crtc *crtc,
-		      struct intel_crtc_state *crtc_state,
-		      struct intel_plane_state *plane_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state);
 void intel_fbc_disable(struct intel_crtc *crtc);
 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Change the calling convention to just pass the state+crtc and
switch to intel_ types throughout.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++-----------
 drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
 drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
 3 files changed, 51 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e341b97b7dec..72655b5b1365 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5920,13 +5920,10 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
  * completely hide the primary plane.
  */
 static void
-intel_post_enable_primary(struct drm_crtc *crtc,
-			  const struct intel_crtc_state *new_crtc_state)
+intel_post_enable_primary(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	/*
 	 * Gen2 reports pipe underruns whenever all planes are disabled.
@@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
-static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
+static void intel_post_plane_update(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
-						crtc);
-	struct drm_plane *primary = crtc->base.primary;
-	struct drm_plane_state *old_primary_state =
-		drm_atomic_get_old_plane_state(state, primary);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_plane_state *old_primary_state =
+		intel_atomic_get_old_plane_state(state, primary);
+	const struct intel_plane_state *new_primary_state =
+		intel_atomic_get_new_plane_state(state, primary);
 
-	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state->fb_bits);
+	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 
 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(crtc);
@@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
 
-	if (old_primary_state) {
-		struct drm_plane_state *new_primary_state =
-			drm_atomic_get_new_plane_state(state, primary);
-
+	if (new_primary_state) {
 		intel_fbc_post_update(crtc);
 
-		if (new_primary_state->visible &&
+		if (new_primary_state->uapi.visible &&
 		    (needs_modeset(new_crtc_state) ||
-		     !old_primary_state->visible))
-			intel_post_enable_primary(&crtc->base, new_crtc_state);
+		     !old_primary_state->uapi.visible))
+			intel_post_enable_primary(crtc);
 	}
 
 	if (needs_nv12_wa(old_crtc_state) &&
@@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
 }
 
-static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
-				   struct intel_crtc_state *new_crtc_state)
+static void intel_pre_plane_update(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct drm_plane *primary = crtc->base.primary;
-	struct drm_plane_state *old_primary_state =
-		drm_atomic_get_old_plane_state(state, primary);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_plane_state *old_primary_state =
+		intel_atomic_get_old_plane_state(state, primary);
+	const struct intel_plane_state *new_primary_state =
+		intel_atomic_get_new_plane_state(state, primary);
 	bool modeset = needs_modeset(new_crtc_state);
-	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(state);
 
 	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
-	if (old_primary_state) {
-		struct intel_plane_state *new_primary_state =
-			intel_atomic_get_new_plane_state(intel_state,
-							 to_intel_plane(primary));
-
+	if (new_primary_state) {
 		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
 		/*
 		 * Gen2 reports pipe underruns whenever all planes are disabled.
 		 * So disable underrun reporting before all the planes get disabled.
 		 */
-		if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
+		if (IS_GEN(dev_priv, 2) && old_primary_state->uapi.visible &&
 		    (modeset || !new_primary_state->uapi.visible))
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 	}
@@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * us to.
 	 */
 	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(intel_state, crtc);
+		dev_priv->display.initial_watermarks(state, crtc);
 	else if (new_crtc_state->update_wm_pre)
 		intel_update_watermarks(crtc);
 }
@@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
 		     new_crtc_state->update_pipe))
 			intel_color_load_luts(new_crtc_state);
 
-		intel_pre_plane_update(old_crtc_state, new_crtc_state);
+		intel_pre_plane_update(state, crtc);
 
 		if (new_crtc_state->update_pipe)
 			intel_encoders_update_pipe(state, crtc);
@@ -14460,7 +14452,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
 		!old_slave_crtc_state);
 
 	/* Disable Slave first */
-	intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+	intel_pre_plane_update(state, slave_crtc);
 	if (old_slave_crtc_state->hw.active)
 		intel_old_crtc_state_disables(state,
 					      old_slave_crtc_state,
@@ -14468,7 +14460,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
 					      slave_crtc);
 
 	/* Disable Master */
-	intel_pre_plane_update(old_crtc_state, new_crtc_state);
+	intel_pre_plane_update(state, crtc);
 	if (old_crtc_state->hw.active)
 		intel_old_crtc_state_disables(state,
 					      old_crtc_state,
@@ -14508,7 +14500,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 			else
 				continue;
 		} else {
-			intel_pre_plane_update(old_crtc_state, new_crtc_state);
+			intel_pre_plane_update(state, crtc);
 
 			if (old_crtc_state->hw.active)
 				intel_old_crtc_state_disables(state,
@@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-		intel_post_plane_update(old_crtc_state);
+		intel_post_plane_update(state, crtc);
 
 		if (put_domains[i])
 			modeset_put_power_domains(dev_priv, put_domains[i]);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 92c7eb243559..70c56abe1a83 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 }
 
 static bool multiple_pipes_ok(struct intel_crtc *crtc,
-			      struct intel_plane_state *plane_state)
+			      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -656,8 +656,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 }
 
 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
-					 struct intel_crtc_state *crtc_state,
-					 struct intel_plane_state *plane_state)
+					 const struct intel_crtc_state *crtc_state,
+					 const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 }
 
 void intel_fbc_pre_update(struct intel_crtc *crtc,
-			  struct intel_crtc_state *crtc_state,
-			  struct intel_plane_state *plane_state)
+			  const struct intel_crtc_state *crtc_state,
+			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
@@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
  * intel_fbc_disable in the middle, as long as it is deactivated.
  */
 void intel_fbc_enable(struct intel_crtc *crtc,
-		      struct intel_crtc_state *crtc_state,
-		      struct intel_plane_state *plane_state)
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 50272eda8d43..f58b0b1e3c5c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 			   struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
 void intel_fbc_pre_update(struct intel_crtc *crtc,
-			  struct intel_crtc_state *crtc_state,
-			  struct intel_plane_state *plane_state);
+			  const struct intel_crtc_state *crtc_state,
+			  const struct intel_plane_state *plane_state);
 void intel_fbc_post_update(struct intel_crtc *crtc);
 void intel_fbc_init(struct drm_i915_private *dev_priv);
 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
 void intel_fbc_enable(struct intel_crtc *crtc,
-		      struct intel_crtc_state *crtc_state,
-		      struct intel_plane_state *plane_state);
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state);
 void intel_fbc_disable(struct intel_crtc *crtc);
 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Change the calling convention to just pass the state+crtc and
> switch to intel_ types throughout.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++---------
> --
>  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
>  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
>  3 files changed, 51 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e341b97b7dec..72655b5b1365 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5920,13 +5920,10 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>   * completely hide the primary plane.
>   */
>  static void
> -intel_post_enable_primary(struct drm_crtc *crtc,
> -			  const struct intel_crtc_state
> *new_crtc_state)
> +intel_post_enable_primary(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  
>  	/*
>  	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct
> intel_crtc_state *crtc_state)
>  	return false;
>  }
>  
> -static void intel_post_plane_update(struct intel_crtc_state
> *old_crtc_state)
> +static void intel_post_plane_update(struct intel_atomic_state
> *state,
> +				    struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> tate),
> -						crtc);
> -	struct drm_plane *primary = crtc->base.primary;
> -	struct drm_plane_state *old_primary_state =
> -		drm_atomic_get_old_plane_state(state, primary);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *primary = to_intel_plane(crtc-
> >base.primary);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_plane_state *old_primary_state =
> +		intel_atomic_get_old_plane_state(state, primary);
> +	const struct intel_plane_state *new_primary_state =
> +		intel_atomic_get_new_plane_state(state, primary);
>  
> -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> >fb_bits);
> +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
>  	if (new_crtc_state->update_wm_post && new_crtc_state-
> >hw.active)
>  		intel_update_watermarks(crtc);
> @@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>  		hsw_enable_ips(new_crtc_state);
>  
> -	if (old_primary_state) {
> -		struct drm_plane_state *new_primary_state =
> -			drm_atomic_get_new_plane_state(state, primary);
> -
> +	if (new_primary_state) {


This change from old_primary_state to new_primary_state is way more
than the commit message says, the change looks right to me but maybe it
deserves a separated patch? Same for the same change in
intel_pre_plane_update()

>  		intel_fbc_post_update(crtc);
>  
> -		if (new_primary_state->visible &&
> +		if (new_primary_state->uapi.visible &&
>  		    (needs_modeset(new_crtc_state) ||
> -		     !old_primary_state->visible))
> -			intel_post_enable_primary(&crtc->base,
> new_crtc_state);
> +		     !old_primary_state->uapi.visible))
> +			intel_post_enable_primary(crtc);
>  	}
>  
>  	if (needs_nv12_wa(old_crtc_state) &&
> @@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
> -static void intel_pre_plane_update(struct intel_crtc_state
> *old_crtc_state,
> -				   struct intel_crtc_state
> *new_crtc_state)
> +static void intel_pre_plane_update(struct intel_atomic_state *state,
> +				   struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct drm_plane *primary = crtc->base.primary;
> -	struct drm_plane_state *old_primary_state =
> -		drm_atomic_get_old_plane_state(state, primary);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *primary = to_intel_plane(crtc-
> >base.primary);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_plane_state *old_primary_state =
> +		intel_atomic_get_old_plane_state(state, primary);
> +	const struct intel_plane_state *new_primary_state =
> +		intel_atomic_get_new_plane_state(state, primary);
>  	bool modeset = needs_modeset(new_crtc_state);
> -	struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(state);
>  
>  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
> -	if (old_primary_state) {
> -		struct intel_plane_state *new_primary_state =
> -			intel_atomic_get_new_plane_state(intel_state,
> -							 to_intel_plane
> (primary));
> -
> +	if (new_primary_state) {
>  		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
>  		/*
>  		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
>  		 * So disable underrun reporting before all the planes
> get disabled.
>  		 */
> -		if (IS_GEN(dev_priv, 2) && old_primary_state->visible
> &&
> +		if (IS_GEN(dev_priv, 2) && old_primary_state-
> >uapi.visible &&
>  		    (modeset || !new_primary_state->uapi.visible))
>  			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, false);
>  	}
> @@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 * us to.
>  	 */
>  	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(intel_state,
> crtc);
> +		dev_priv->display.initial_watermarks(state, crtc);
>  	else if (new_crtc_state->update_wm_pre)
>  		intel_update_watermarks(crtc);
>  }
> @@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct
> intel_crtc *crtc,
>  		     new_crtc_state->update_pipe))
>  			intel_color_load_luts(new_crtc_state);
>  
> -		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> +		intel_pre_plane_update(state, crtc);
>  
>  		if (new_crtc_state->update_pipe)
>  			intel_encoders_update_pipe(state, crtc);
> @@ -14460,7 +14452,7 @@ static void
> intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
>  		!old_slave_crtc_state);
>  
>  	/* Disable Slave first */
> -	intel_pre_plane_update(old_slave_crtc_state,
> new_slave_crtc_state);
> +	intel_pre_plane_update(state, slave_crtc);
>  	if (old_slave_crtc_state->hw.active)
>  		intel_old_crtc_state_disables(state,
>  					      old_slave_crtc_state,
> @@ -14468,7 +14460,7 @@ static void
> intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
>  					      slave_crtc);
>  
>  	/* Disable Master */
> -	intel_pre_plane_update(old_crtc_state, new_crtc_state);
> +	intel_pre_plane_update(state, crtc);
>  	if (old_crtc_state->hw.active)
>  		intel_old_crtc_state_disables(state,
>  					      old_crtc_state,
> @@ -14508,7 +14500,7 @@ static void
> intel_commit_modeset_disables(struct intel_atomic_state *state)
>  			else
>  				continue;
>  		} else {
> -			intel_pre_plane_update(old_crtc_state,
> new_crtc_state);
> +			intel_pre_plane_update(state, crtc);
>  
>  			if (old_crtc_state->hw.active)
>  				intel_old_crtc_state_disables(state,
> @@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	}
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state, new_crtc_state, i) {
> -		intel_post_plane_update(old_crtc_state);
> +		intel_post_plane_update(state, crtc);
>  
>  		if (put_domains[i])
>  			modeset_put_power_domains(dev_priv,
> put_domains[i]);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 92c7eb243559..70c56abe1a83 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct
> drm_i915_private *dev_priv,
>  }
>  
>  static bool multiple_pipes_ok(struct intel_crtc *crtc,
> -			      struct intel_plane_state *plane_state)
> +			      const struct intel_plane_state
> *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -656,8 +656,8 @@ static bool
> intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  }
>  
>  static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> -					 struct intel_crtc_state
> *crtc_state,
> -					 struct intel_plane_state
> *plane_state)
> +					 const struct intel_crtc_state
> *crtc_state,
> +					 const struct intel_plane_state
> *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct
> intel_crtc *crtc,
>  }
>  
>  void intel_fbc_pre_update(struct intel_crtc *crtc,
> -			  struct intel_crtc_state *crtc_state,
> -			  struct intel_plane_state *plane_state)
> +			  const struct intel_crtc_state *crtc_state,
> +			  const struct intel_plane_state *plane_state)

Nice

Other than the first comment, LGTM.

>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct
> drm_i915_private *dev_priv,
>   * intel_fbc_disable in the middle, as long as it is deactivated.
>   */
>  void intel_fbc_enable(struct intel_crtc *crtc,
> -		      struct intel_crtc_state *crtc_state,
> -		      struct intel_plane_state *plane_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 50272eda8d43..f58b0b1e3c5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct
> drm_i915_private *dev_priv,
>  			   struct intel_atomic_state *state);
>  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
>  void intel_fbc_pre_update(struct intel_crtc *crtc,
> -			  struct intel_crtc_state *crtc_state,
> -			  struct intel_plane_state *plane_state);
> +			  const struct intel_crtc_state *crtc_state,
> +			  const struct intel_plane_state *plane_state);
>  void intel_fbc_post_update(struct intel_crtc *crtc);
>  void intel_fbc_init(struct drm_i915_private *dev_priv);
>  void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
>  void intel_fbc_enable(struct intel_crtc *crtc,
> -		      struct intel_crtc_state *crtc_state,
> -		      struct intel_plane_state *plane_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state);
>  void intel_fbc_disable(struct intel_crtc *crtc);
>  void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
>  void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Change the calling convention to just pass the state+crtc and
> switch to intel_ types throughout.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++---------
> --
>  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
>  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
>  3 files changed, 51 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e341b97b7dec..72655b5b1365 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5920,13 +5920,10 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>   * completely hide the primary plane.
>   */
>  static void
> -intel_post_enable_primary(struct drm_crtc *crtc,
> -			  const struct intel_crtc_state
> *new_crtc_state)
> +intel_post_enable_primary(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  
>  	/*
>  	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct
> intel_crtc_state *crtc_state)
>  	return false;
>  }
>  
> -static void intel_post_plane_update(struct intel_crtc_state
> *old_crtc_state)
> +static void intel_post_plane_update(struct intel_atomic_state
> *state,
> +				    struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> tate),
> -						crtc);
> -	struct drm_plane *primary = crtc->base.primary;
> -	struct drm_plane_state *old_primary_state =
> -		drm_atomic_get_old_plane_state(state, primary);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *primary = to_intel_plane(crtc-
> >base.primary);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_plane_state *old_primary_state =
> +		intel_atomic_get_old_plane_state(state, primary);
> +	const struct intel_plane_state *new_primary_state =
> +		intel_atomic_get_new_plane_state(state, primary);
>  
> -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> >fb_bits);
> +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
>  	if (new_crtc_state->update_wm_post && new_crtc_state-
> >hw.active)
>  		intel_update_watermarks(crtc);
> @@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>  		hsw_enable_ips(new_crtc_state);
>  
> -	if (old_primary_state) {
> -		struct drm_plane_state *new_primary_state =
> -			drm_atomic_get_new_plane_state(state, primary);
> -
> +	if (new_primary_state) {


This change from old_primary_state to new_primary_state is way more
than the commit message says, the change looks right to me but maybe it
deserves a separated patch? Same for the same change in
intel_pre_plane_update()

>  		intel_fbc_post_update(crtc);
>  
> -		if (new_primary_state->visible &&
> +		if (new_primary_state->uapi.visible &&
>  		    (needs_modeset(new_crtc_state) ||
> -		     !old_primary_state->visible))
> -			intel_post_enable_primary(&crtc->base,
> new_crtc_state);
> +		     !old_primary_state->uapi.visible))
> +			intel_post_enable_primary(crtc);
>  	}
>  
>  	if (needs_nv12_wa(old_crtc_state) &&
> @@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
>  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
>  }
>  
> -static void intel_pre_plane_update(struct intel_crtc_state
> *old_crtc_state,
> -				   struct intel_crtc_state
> *new_crtc_state)
> +static void intel_pre_plane_update(struct intel_atomic_state *state,
> +				   struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> -	struct drm_plane *primary = crtc->base.primary;
> -	struct drm_plane_state *old_primary_state =
> -		drm_atomic_get_old_plane_state(state, primary);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *primary = to_intel_plane(crtc-
> >base.primary);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_plane_state *old_primary_state =
> +		intel_atomic_get_old_plane_state(state, primary);
> +	const struct intel_plane_state *new_primary_state =
> +		intel_atomic_get_new_plane_state(state, primary);
>  	bool modeset = needs_modeset(new_crtc_state);
> -	struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(state);
>  
>  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
> -	if (old_primary_state) {
> -		struct intel_plane_state *new_primary_state =
> -			intel_atomic_get_new_plane_state(intel_state,
> -							 to_intel_plane
> (primary));
> -
> +	if (new_primary_state) {
>  		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
>  		/*
>  		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
>  		 * So disable underrun reporting before all the planes
> get disabled.
>  		 */
> -		if (IS_GEN(dev_priv, 2) && old_primary_state->visible
> &&
> +		if (IS_GEN(dev_priv, 2) && old_primary_state-
> >uapi.visible &&
>  		    (modeset || !new_primary_state->uapi.visible))
>  			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, false);
>  	}
> @@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>  	 * us to.
>  	 */
>  	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(intel_state,
> crtc);
> +		dev_priv->display.initial_watermarks(state, crtc);
>  	else if (new_crtc_state->update_wm_pre)
>  		intel_update_watermarks(crtc);
>  }
> @@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct
> intel_crtc *crtc,
>  		     new_crtc_state->update_pipe))
>  			intel_color_load_luts(new_crtc_state);
>  
> -		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> +		intel_pre_plane_update(state, crtc);
>  
>  		if (new_crtc_state->update_pipe)
>  			intel_encoders_update_pipe(state, crtc);
> @@ -14460,7 +14452,7 @@ static void
> intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
>  		!old_slave_crtc_state);
>  
>  	/* Disable Slave first */
> -	intel_pre_plane_update(old_slave_crtc_state,
> new_slave_crtc_state);
> +	intel_pre_plane_update(state, slave_crtc);
>  	if (old_slave_crtc_state->hw.active)
>  		intel_old_crtc_state_disables(state,
>  					      old_slave_crtc_state,
> @@ -14468,7 +14460,7 @@ static void
> intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
>  					      slave_crtc);
>  
>  	/* Disable Master */
> -	intel_pre_plane_update(old_crtc_state, new_crtc_state);
> +	intel_pre_plane_update(state, crtc);
>  	if (old_crtc_state->hw.active)
>  		intel_old_crtc_state_disables(state,
>  					      old_crtc_state,
> @@ -14508,7 +14500,7 @@ static void
> intel_commit_modeset_disables(struct intel_atomic_state *state)
>  			else
>  				continue;
>  		} else {
> -			intel_pre_plane_update(old_crtc_state,
> new_crtc_state);
> +			intel_pre_plane_update(state, crtc);
>  
>  			if (old_crtc_state->hw.active)
>  				intel_old_crtc_state_disables(state,
> @@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	}
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state, new_crtc_state, i) {
> -		intel_post_plane_update(old_crtc_state);
> +		intel_post_plane_update(state, crtc);
>  
>  		if (put_domains[i])
>  			modeset_put_power_domains(dev_priv,
> put_domains[i]);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 92c7eb243559..70c56abe1a83 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct
> drm_i915_private *dev_priv,
>  }
>  
>  static bool multiple_pipes_ok(struct intel_crtc *crtc,
> -			      struct intel_plane_state *plane_state)
> +			      const struct intel_plane_state
> *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -656,8 +656,8 @@ static bool
> intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  }
>  
>  static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> -					 struct intel_crtc_state
> *crtc_state,
> -					 struct intel_plane_state
> *plane_state)
> +					 const struct intel_crtc_state
> *crtc_state,
> +					 const struct intel_plane_state
> *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct
> intel_crtc *crtc,
>  }
>  
>  void intel_fbc_pre_update(struct intel_crtc *crtc,
> -			  struct intel_crtc_state *crtc_state,
> -			  struct intel_plane_state *plane_state)
> +			  const struct intel_crtc_state *crtc_state,
> +			  const struct intel_plane_state *plane_state)

Nice

Other than the first comment, LGTM.

>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> @@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct
> drm_i915_private *dev_priv,
>   * intel_fbc_disable in the middle, as long as it is deactivated.
>   */
>  void intel_fbc_enable(struct intel_crtc *crtc,
> -		      struct intel_crtc_state *crtc_state,
> -		      struct intel_plane_state *plane_state)
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 50272eda8d43..f58b0b1e3c5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct
> drm_i915_private *dev_priv,
>  			   struct intel_atomic_state *state);
>  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
>  void intel_fbc_pre_update(struct intel_crtc *crtc,
> -			  struct intel_crtc_state *crtc_state,
> -			  struct intel_plane_state *plane_state);
> +			  const struct intel_crtc_state *crtc_state,
> +			  const struct intel_plane_state *plane_state);
>  void intel_fbc_post_update(struct intel_crtc *crtc);
>  void intel_fbc_init(struct drm_i915_private *dev_priv);
>  void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
>  void intel_fbc_enable(struct intel_crtc *crtc,
> -		      struct intel_crtc_state *crtc_state,
> -		      struct intel_plane_state *plane_state);
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state);
>  void intel_fbc_disable(struct intel_crtc *crtc);
>  void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
>  void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Ville Syrjälä]

On Wed, Nov 27, 2019 at 11:25:07PM +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Change the calling convention to just pass the state+crtc and
> > switch to intel_ types throughout.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++---------
> > --
> >  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
> >  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
> >  3 files changed, 51 insertions(+), 59 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e341b97b7dec..72655b5b1365 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5920,13 +5920,10 @@ static void
> > intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
> >   * completely hide the primary plane.
> >   */
> >  static void
> > -intel_post_enable_primary(struct drm_crtc *crtc,
> > -			  const struct intel_crtc_state
> > *new_crtc_state)
> > +intel_post_enable_primary(struct intel_crtc *crtc)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> >  
> >  	/*
> >  	 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> > @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct
> > intel_crtc_state *crtc_state)
> >  	return false;
> >  }
> >  
> > -static void intel_post_plane_update(struct intel_crtc_state
> > *old_crtc_state)
> > +static void intel_post_plane_update(struct intel_atomic_state
> > *state,
> > +				    struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > >uapi.crtc);
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct intel_crtc_state *new_crtc_state =
> > -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > tate),
> > -						crtc);
> > -	struct drm_plane *primary = crtc->base.primary;
> > -	struct drm_plane_state *old_primary_state =
> > -		drm_atomic_get_old_plane_state(state, primary);
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_plane *primary = to_intel_plane(crtc-
> > >base.primary);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct intel_plane_state *old_primary_state =
> > +		intel_atomic_get_old_plane_state(state, primary);
> > +	const struct intel_plane_state *new_primary_state =
> > +		intel_atomic_get_new_plane_state(state, primary);
> >  
> > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > >fb_bits);
> > +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
> >  
> >  	if (new_crtc_state->update_wm_post && new_crtc_state-
> > >hw.active)
> >  		intel_update_watermarks(crtc);
> > @@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_enable_ips(new_crtc_state);
> >  
> > -	if (old_primary_state) {
> > -		struct drm_plane_state *new_primary_state =
> > -			drm_atomic_get_new_plane_state(state, primary);
> > -
> > +	if (new_primary_state) {
> 
> 
> This change from old_primary_state to new_primary_state is way more
> than the commit message says, the change looks right to me but maybe it
> deserves a separated patch? Same for the same change in
> intel_pre_plane_update()

I wanted to change it so I can eliminate old_primary_state in
a subsequent patch. For whatever reason that change slipped
into this patch. It's a nop change though since
!new_state == !old_state always.

> 
> >  		intel_fbc_post_update(crtc);
> >  
> > -		if (new_primary_state->visible &&
> > +		if (new_primary_state->uapi.visible &&
> >  		    (needs_modeset(new_crtc_state) ||
> > -		     !old_primary_state->visible))
> > -			intel_post_enable_primary(&crtc->base,
> > new_crtc_state);
> > +		     !old_primary_state->uapi.visible))
> > +			intel_post_enable_primary(crtc);
> >  	}
> >  
> >  	if (needs_nv12_wa(old_crtc_state) &&
> > @@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> >  }
> >  
> > -static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > -				   struct intel_crtc_state
> > *new_crtc_state)
> > +static void intel_pre_plane_update(struct intel_atomic_state *state,
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > >uapi.crtc);
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct drm_plane *primary = crtc->base.primary;
> > -	struct drm_plane_state *old_primary_state =
> > -		drm_atomic_get_old_plane_state(state, primary);
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_plane *primary = to_intel_plane(crtc-
> > >base.primary);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct intel_plane_state *old_primary_state =
> > +		intel_atomic_get_old_plane_state(state, primary);
> > +	const struct intel_plane_state *new_primary_state =
> > +		intel_atomic_get_new_plane_state(state, primary);
> >  	bool modeset = needs_modeset(new_crtc_state);
> > -	struct intel_atomic_state *intel_state =
> > -		to_intel_atomic_state(state);
> >  
> >  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_disable_ips(old_crtc_state);
> >  
> > -	if (old_primary_state) {
> > -		struct intel_plane_state *new_primary_state =
> > -			intel_atomic_get_new_plane_state(intel_state,
> > -							 to_intel_plane
> > (primary));
> > -
> > +	if (new_primary_state) {
> >  		intel_fbc_pre_update(crtc, new_crtc_state,
> > new_primary_state);
> >  		/*
> >  		 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> >  		 * So disable underrun reporting before all the planes
> > get disabled.
> >  		 */
> > -		if (IS_GEN(dev_priv, 2) && old_primary_state->visible
> > &&
> > +		if (IS_GEN(dev_priv, 2) && old_primary_state-
> > >uapi.visible &&
> >  		    (modeset || !new_primary_state->uapi.visible))
> >  			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> > crtc->pipe, false);
> >  	}
> > @@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 * us to.
> >  	 */
> >  	if (dev_priv->display.initial_watermarks)
> > -		dev_priv->display.initial_watermarks(intel_state,
> > crtc);
> > +		dev_priv->display.initial_watermarks(state, crtc);
> >  	else if (new_crtc_state->update_wm_pre)
> >  		intel_update_watermarks(crtc);
> >  }
> > @@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct
> > intel_crtc *crtc,
> >  		     new_crtc_state->update_pipe))
> >  			intel_color_load_luts(new_crtc_state);
> >  
> > -		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > +		intel_pre_plane_update(state, crtc);
> >  
> >  		if (new_crtc_state->update_pipe)
> >  			intel_encoders_update_pipe(state, crtc);
> > @@ -14460,7 +14452,7 @@ static void
> > intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
> >  		!old_slave_crtc_state);
> >  
> >  	/* Disable Slave first */
> > -	intel_pre_plane_update(old_slave_crtc_state,
> > new_slave_crtc_state);
> > +	intel_pre_plane_update(state, slave_crtc);
> >  	if (old_slave_crtc_state->hw.active)
> >  		intel_old_crtc_state_disables(state,
> >  					      old_slave_crtc_state,
> > @@ -14468,7 +14460,7 @@ static void
> > intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
> >  					      slave_crtc);
> >  
> >  	/* Disable Master */
> > -	intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > +	intel_pre_plane_update(state, crtc);
> >  	if (old_crtc_state->hw.active)
> >  		intel_old_crtc_state_disables(state,
> >  					      old_crtc_state,
> > @@ -14508,7 +14500,7 @@ static void
> > intel_commit_modeset_disables(struct intel_atomic_state *state)
> >  			else
> >  				continue;
> >  		} else {
> > -			intel_pre_plane_update(old_crtc_state,
> > new_crtc_state);
> > +			intel_pre_plane_update(state, crtc);
> >  
> >  			if (old_crtc_state->hw.active)
> >  				intel_old_crtc_state_disables(state,
> > @@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  	}
> >  
> >  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> > -		intel_post_plane_update(old_crtc_state);
> > +		intel_post_plane_update(state, crtc);
> >  
> >  		if (put_domains[i])
> >  			modeset_put_power_domains(dev_priv,
> > put_domains[i]);
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 92c7eb243559..70c56abe1a83 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct
> > drm_i915_private *dev_priv,
> >  }
> >  
> >  static bool multiple_pipes_ok(struct intel_crtc *crtc,
> > -			      struct intel_plane_state *plane_state)
> > +			      const struct intel_plane_state
> > *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -656,8 +656,8 @@ static bool
> > intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
> >  }
> >  
> >  static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > -					 struct intel_crtc_state
> > *crtc_state,
> > -					 struct intel_plane_state
> > *plane_state)
> > +					 const struct intel_crtc_state
> > *crtc_state,
> > +					 const struct intel_plane_state
> > *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct
> > intel_crtc *crtc,
> >  }
> >  
> >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > -			  struct intel_crtc_state *crtc_state,
> > -			  struct intel_plane_state *plane_state)
> > +			  const struct intel_crtc_state *crtc_state,
> > +			  const struct intel_plane_state *plane_state)
> 
> Nice
> 
> Other than the first comment, LGTM.
> 
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct
> > drm_i915_private *dev_priv,
> >   * intel_fbc_disable in the middle, as long as it is deactivated.
> >   */
> >  void intel_fbc_enable(struct intel_crtc *crtc,
> > -		      struct intel_crtc_state *crtc_state,
> > -		      struct intel_plane_state *plane_state)
> > +		      const struct intel_crtc_state *crtc_state,
> > +		      const struct intel_plane_state *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index 50272eda8d43..f58b0b1e3c5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct
> > drm_i915_private *dev_priv,
> >  			   struct intel_atomic_state *state);
> >  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > -			  struct intel_crtc_state *crtc_state,
> > -			  struct intel_plane_state *plane_state);
> > +			  const struct intel_crtc_state *crtc_state,
> > +			  const struct intel_plane_state *plane_state);
> >  void intel_fbc_post_update(struct intel_crtc *crtc);
> >  void intel_fbc_init(struct drm_i915_private *dev_priv);
> >  void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
> >  void intel_fbc_enable(struct intel_crtc *crtc,
> > -		      struct intel_crtc_state *crtc_state,
> > -		      struct intel_plane_state *plane_state);
> > +		      const struct intel_crtc_state *crtc_state,
> > +		      const struct intel_plane_state *plane_state);
> >  void intel_fbc_disable(struct intel_crtc *crtc);
> >  void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
> >  void intel_fbc_invalidate(struct drm_i915_private *dev_priv,

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Ville Syrjälä]

On Wed, Nov 27, 2019 at 11:25:07PM +0000, Souza, Jose wrote:
> On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Change the calling convention to just pass the state+crtc and
> > switch to intel_ types throughout.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++---------
> > --
> >  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
> >  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
> >  3 files changed, 51 insertions(+), 59 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e341b97b7dec..72655b5b1365 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5920,13 +5920,10 @@ static void
> > intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
> >   * completely hide the primary plane.
> >   */
> >  static void
> > -intel_post_enable_primary(struct drm_crtc *crtc,
> > -			  const struct intel_crtc_state
> > *new_crtc_state)
> > +intel_post_enable_primary(struct intel_crtc *crtc)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> >  
> >  	/*
> >  	 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> > @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const struct
> > intel_crtc_state *crtc_state)
> >  	return false;
> >  }
> >  
> > -static void intel_post_plane_update(struct intel_crtc_state
> > *old_crtc_state)
> > +static void intel_post_plane_update(struct intel_atomic_state
> > *state,
> > +				    struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > >uapi.crtc);
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct intel_crtc_state *new_crtc_state =
> > -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > tate),
> > -						crtc);
> > -	struct drm_plane *primary = crtc->base.primary;
> > -	struct drm_plane_state *old_primary_state =
> > -		drm_atomic_get_old_plane_state(state, primary);
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_plane *primary = to_intel_plane(crtc-
> > >base.primary);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct intel_plane_state *old_primary_state =
> > +		intel_atomic_get_old_plane_state(state, primary);
> > +	const struct intel_plane_state *new_primary_state =
> > +		intel_atomic_get_new_plane_state(state, primary);
> >  
> > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > >fb_bits);
> > +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
> >  
> >  	if (new_crtc_state->update_wm_post && new_crtc_state-
> > >hw.active)
> >  		intel_update_watermarks(crtc);
> > @@ -6083,16 +6081,13 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_enable_ips(new_crtc_state);
> >  
> > -	if (old_primary_state) {
> > -		struct drm_plane_state *new_primary_state =
> > -			drm_atomic_get_new_plane_state(state, primary);
> > -
> > +	if (new_primary_state) {
> 
> 
> This change from old_primary_state to new_primary_state is way more
> than the commit message says, the change looks right to me but maybe it
> deserves a separated patch? Same for the same change in
> intel_pre_plane_update()

I wanted to change it so I can eliminate old_primary_state in
a subsequent patch. For whatever reason that change slipped
into this patch. It's a nop change though since
!new_state == !old_state always.

> 
> >  		intel_fbc_post_update(crtc);
> >  
> > -		if (new_primary_state->visible &&
> > +		if (new_primary_state->uapi.visible &&
> >  		    (needs_modeset(new_crtc_state) ||
> > -		     !old_primary_state->visible))
> > -			intel_post_enable_primary(&crtc->base,
> > new_crtc_state);
> > +		     !old_primary_state->uapi.visible))
> > +			intel_post_enable_primary(crtc);
> >  	}
> >  
> >  	if (needs_nv12_wa(old_crtc_state) &&
> > @@ -6104,34 +6099,31 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> >  }
> >  
> > -static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > -				   struct intel_crtc_state
> > *new_crtc_state)
> > +static void intel_pre_plane_update(struct intel_atomic_state *state,
> > +				   struct intel_crtc *crtc)
> >  {
> > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > >uapi.crtc);
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > -	struct drm_plane *primary = crtc->base.primary;
> > -	struct drm_plane_state *old_primary_state =
> > -		drm_atomic_get_old_plane_state(state, primary);
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_plane *primary = to_intel_plane(crtc-
> > >base.primary);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *new_crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct intel_plane_state *old_primary_state =
> > +		intel_atomic_get_old_plane_state(state, primary);
> > +	const struct intel_plane_state *new_primary_state =
> > +		intel_atomic_get_new_plane_state(state, primary);
> >  	bool modeset = needs_modeset(new_crtc_state);
> > -	struct intel_atomic_state *intel_state =
> > -		to_intel_atomic_state(state);
> >  
> >  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> >  		hsw_disable_ips(old_crtc_state);
> >  
> > -	if (old_primary_state) {
> > -		struct intel_plane_state *new_primary_state =
> > -			intel_atomic_get_new_plane_state(intel_state,
> > -							 to_intel_plane
> > (primary));
> > -
> > +	if (new_primary_state) {
> >  		intel_fbc_pre_update(crtc, new_crtc_state,
> > new_primary_state);
> >  		/*
> >  		 * Gen2 reports pipe underruns whenever all planes are
> > disabled.
> >  		 * So disable underrun reporting before all the planes
> > get disabled.
> >  		 */
> > -		if (IS_GEN(dev_priv, 2) && old_primary_state->visible
> > &&
> > +		if (IS_GEN(dev_priv, 2) && old_primary_state-
> > >uapi.visible &&
> >  		    (modeset || !new_primary_state->uapi.visible))
> >  			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> > crtc->pipe, false);
> >  	}
> > @@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  	 * us to.
> >  	 */
> >  	if (dev_priv->display.initial_watermarks)
> > -		dev_priv->display.initial_watermarks(intel_state,
> > crtc);
> > +		dev_priv->display.initial_watermarks(state, crtc);
> >  	else if (new_crtc_state->update_wm_pre)
> >  		intel_update_watermarks(crtc);
> >  }
> > @@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct
> > intel_crtc *crtc,
> >  		     new_crtc_state->update_pipe))
> >  			intel_color_load_luts(new_crtc_state);
> >  
> > -		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > +		intel_pre_plane_update(state, crtc);
> >  
> >  		if (new_crtc_state->update_pipe)
> >  			intel_encoders_update_pipe(state, crtc);
> > @@ -14460,7 +14452,7 @@ static void
> > intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
> >  		!old_slave_crtc_state);
> >  
> >  	/* Disable Slave first */
> > -	intel_pre_plane_update(old_slave_crtc_state,
> > new_slave_crtc_state);
> > +	intel_pre_plane_update(state, slave_crtc);
> >  	if (old_slave_crtc_state->hw.active)
> >  		intel_old_crtc_state_disables(state,
> >  					      old_slave_crtc_state,
> > @@ -14468,7 +14460,7 @@ static void
> > intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
> >  					      slave_crtc);
> >  
> >  	/* Disable Master */
> > -	intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > +	intel_pre_plane_update(state, crtc);
> >  	if (old_crtc_state->hw.active)
> >  		intel_old_crtc_state_disables(state,
> >  					      old_crtc_state,
> > @@ -14508,7 +14500,7 @@ static void
> > intel_commit_modeset_disables(struct intel_atomic_state *state)
> >  			else
> >  				continue;
> >  		} else {
> > -			intel_pre_plane_update(old_crtc_state,
> > new_crtc_state);
> > +			intel_pre_plane_update(state, crtc);
> >  
> >  			if (old_crtc_state->hw.active)
> >  				intel_old_crtc_state_disables(state,
> > @@ -14896,7 +14888,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  	}
> >  
> >  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> > -		intel_post_plane_update(old_crtc_state);
> > +		intel_post_plane_update(state, crtc);
> >  
> >  		if (put_domains[i])
> >  			modeset_put_power_domains(dev_priv,
> > put_domains[i]);
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 92c7eb243559..70c56abe1a83 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct
> > drm_i915_private *dev_priv,
> >  }
> >  
> >  static bool multiple_pipes_ok(struct intel_crtc *crtc,
> > -			      struct intel_plane_state *plane_state)
> > +			      const struct intel_plane_state
> > *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -656,8 +656,8 @@ static bool
> > intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
> >  }
> >  
> >  static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > -					 struct intel_crtc_state
> > *crtc_state,
> > -					 struct intel_plane_state
> > *plane_state)
> > +					 const struct intel_crtc_state
> > *crtc_state,
> > +					 const struct intel_plane_state
> > *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct
> > intel_crtc *crtc,
> >  }
> >  
> >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > -			  struct intel_crtc_state *crtc_state,
> > -			  struct intel_plane_state *plane_state)
> > +			  const struct intel_crtc_state *crtc_state,
> > +			  const struct intel_plane_state *plane_state)
> 
> Nice
> 
> Other than the first comment, LGTM.
> 
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > @@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct
> > drm_i915_private *dev_priv,
> >   * intel_fbc_disable in the middle, as long as it is deactivated.
> >   */
> >  void intel_fbc_enable(struct intel_crtc *crtc,
> > -		      struct intel_crtc_state *crtc_state,
> > -		      struct intel_plane_state *plane_state)
> > +		      const struct intel_crtc_state *crtc_state,
> > +		      const struct intel_plane_state *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index 50272eda8d43..f58b0b1e3c5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct
> > drm_i915_private *dev_priv,
> >  			   struct intel_atomic_state *state);
> >  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > -			  struct intel_crtc_state *crtc_state,
> > -			  struct intel_plane_state *plane_state);
> > +			  const struct intel_crtc_state *crtc_state,
> > +			  const struct intel_plane_state *plane_state);
> >  void intel_fbc_post_update(struct intel_crtc *crtc);
> >  void intel_fbc_init(struct drm_i915_private *dev_priv);
> >  void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
> >  void intel_fbc_enable(struct intel_crtc *crtc,
> > -		      struct intel_crtc_state *crtc_state,
> > -		      struct intel_plane_state *plane_state);
> > +		      const struct intel_crtc_state *crtc_state,
> > +		      const struct intel_plane_state *plane_state);
> >  void intel_fbc_disable(struct intel_crtc *crtc);
> >  void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
> >  void intel_fbc_invalidate(struct drm_i915_private *dev_priv,

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Souza, Jose]

On Thu, 2019-11-28 at 14:02 +0200, Ville Syrjälä wrote:
> On Wed, Nov 27, 2019 at 11:25:07PM +0000, Souza, Jose wrote:
> > On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Change the calling convention to just pass the state+crtc and
> > > switch to intel_ types throughout.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++-----
> > > ----
> > > --
> > >  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
> > >  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
> > >  3 files changed, 51 insertions(+), 59 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e341b97b7dec..72655b5b1365 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -5920,13 +5920,10 @@ static void
> > > intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
> > >   * completely hide the primary plane.
> > >   */
> > >  static void
> > > -intel_post_enable_primary(struct drm_crtc *crtc,
> > > -			  const struct intel_crtc_state
> > > *new_crtc_state)
> > > +intel_post_enable_primary(struct intel_crtc *crtc)
> > >  {
> > > -	struct drm_device *dev = crtc->dev;
> > > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > -	enum pipe pipe = intel_crtc->pipe;
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > +	enum pipe pipe = crtc->pipe;
> > >  
> > >  	/*
> > >  	 * Gen2 reports pipe underruns whenever all planes are
> > > disabled.
> > > @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const
> > > struct
> > > intel_crtc_state *crtc_state)
> > >  	return false;
> > >  }
> > >  
> > > -static void intel_post_plane_update(struct intel_crtc_state
> > > *old_crtc_state)
> > > +static void intel_post_plane_update(struct intel_atomic_state
> > > *state,
> > > +				    struct intel_crtc *crtc)
> > >  {
> > > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > > uapi.crtc);
> > > -	struct drm_device *dev = crtc->base.dev;
> > > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > > -	struct intel_crtc_state *new_crtc_state =
> > > -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > > tate),
> > > -						crtc);
> > > -	struct drm_plane *primary = crtc->base.primary;
> > > -	struct drm_plane_state *old_primary_state =
> > > -		drm_atomic_get_old_plane_state(state, primary);
> > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > +	struct intel_plane *primary = to_intel_plane(crtc-
> > > > base.primary);
> > > +	const struct intel_crtc_state *old_crtc_state =
> > > +		intel_atomic_get_old_crtc_state(state, crtc);
> > > +	const struct intel_crtc_state *new_crtc_state =
> > > +		intel_atomic_get_new_crtc_state(state, crtc);
> > > +	const struct intel_plane_state *old_primary_state =
> > > +		intel_atomic_get_old_plane_state(state, primary);
> > > +	const struct intel_plane_state *new_primary_state =
> > > +		intel_atomic_get_new_plane_state(state, primary);
> > >  
> > > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > > > fb_bits);
> > > +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
> > >  
> > >  	if (new_crtc_state->update_wm_post && new_crtc_state-
> > > > hw.active)
> > >  		intel_update_watermarks(crtc);
> > > @@ -6083,16 +6081,13 @@ static void
> > > intel_post_plane_update(struct
> > > intel_crtc_state *old_crtc_state)
> > >  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> > >  		hsw_enable_ips(new_crtc_state);
> > >  
> > > -	if (old_primary_state) {
> > > -		struct drm_plane_state *new_primary_state =
> > > -			drm_atomic_get_new_plane_state(state, primary);
> > > -
> > > +	if (new_primary_state) {
> > 
> > This change from old_primary_state to new_primary_state is way more
> > than the commit message says, the change looks right to me but
> > maybe it
> > deserves a separated patch? Same for the same change in
> > intel_pre_plane_update()
> 
> I wanted to change it so I can eliminate old_primary_state in
> a subsequent patch. For whatever reason that change slipped
> into this patch. It's a nop change though since
> !new_state == !old_state always.

Maybe worthy to mention it in the description?! Will leave that up to
you.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> > >  		intel_fbc_post_update(crtc);
> > >  
> > > -		if (new_primary_state->visible &&
> > > +		if (new_primary_state->uapi.visible &&
> > >  		    (needs_modeset(new_crtc_state) ||
> > > -		     !old_primary_state->visible))
> > > -			intel_post_enable_primary(&crtc->base,
> > > new_crtc_state);
> > > +		     !old_primary_state->uapi.visible))
> > > +			intel_post_enable_primary(crtc);
> > >  	}
> > >  
> > >  	if (needs_nv12_wa(old_crtc_state) &&
> > > @@ -6104,34 +6099,31 @@ static void
> > > intel_post_plane_update(struct
> > > intel_crtc_state *old_crtc_state)
> > >  		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> > >  }
> > >  
> > > -static void intel_pre_plane_update(struct intel_crtc_state
> > > *old_crtc_state,
> > > -				   struct intel_crtc_state
> > > *new_crtc_state)
> > > +static void intel_pre_plane_update(struct intel_atomic_state
> > > *state,
> > > +				   struct intel_crtc *crtc)
> > >  {
> > > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > > uapi.crtc);
> > > -	struct drm_device *dev = crtc->base.dev;
> > > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > > -	struct drm_plane *primary = crtc->base.primary;
> > > -	struct drm_plane_state *old_primary_state =
> > > -		drm_atomic_get_old_plane_state(state, primary);
> > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > +	struct intel_plane *primary = to_intel_plane(crtc-
> > > > base.primary);
> > > +	const struct intel_crtc_state *old_crtc_state =
> > > +		intel_atomic_get_old_crtc_state(state, crtc);
> > > +	const struct intel_crtc_state *new_crtc_state =
> > > +		intel_atomic_get_new_crtc_state(state, crtc);
> > > +	const struct intel_plane_state *old_primary_state =
> > > +		intel_atomic_get_old_plane_state(state, primary);
> > > +	const struct intel_plane_state *new_primary_state =
> > > +		intel_atomic_get_new_plane_state(state, primary);
> > >  	bool modeset = needs_modeset(new_crtc_state);
> > > -	struct intel_atomic_state *intel_state =
> > > -		to_intel_atomic_state(state);
> > >  
> > >  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> > >  		hsw_disable_ips(old_crtc_state);
> > >  
> > > -	if (old_primary_state) {
> > > -		struct intel_plane_state *new_primary_state =
> > > -			intel_atomic_get_new_plane_state(intel_state,
> > > -							 to_intel_plane
> > > (primary));
> > > -
> > > +	if (new_primary_state) {
> > >  		intel_fbc_pre_update(crtc, new_crtc_state,
> > > new_primary_state);
> > >  		/*
> > >  		 * Gen2 reports pipe underruns whenever all planes are
> > > disabled.
> > >  		 * So disable underrun reporting before all the planes
> > > get disabled.
> > >  		 */
> > > -		if (IS_GEN(dev_priv, 2) && old_primary_state->visible
> > > &&
> > > +		if (IS_GEN(dev_priv, 2) && old_primary_state-
> > > > uapi.visible &&
> > >  		    (modeset || !new_primary_state->uapi.visible))
> > >  			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> > > crtc->pipe, false);
> > >  	}
> > > @@ -6192,7 +6184,7 @@ static void intel_pre_plane_update(struct
> > > intel_crtc_state *old_crtc_state,
> > >  	 * us to.
> > >  	 */
> > >  	if (dev_priv->display.initial_watermarks)
> > > -		dev_priv->display.initial_watermarks(intel_state,
> > > crtc);
> > > +		dev_priv->display.initial_watermarks(state, crtc);
> > >  	else if (new_crtc_state->update_wm_pre)
> > >  		intel_update_watermarks(crtc);
> > >  }
> > > @@ -14365,7 +14357,7 @@ static void intel_update_crtc(struct
> > > intel_crtc *crtc,
> > >  		     new_crtc_state->update_pipe))
> > >  			intel_color_load_luts(new_crtc_state);
> > >  
> > > -		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > > +		intel_pre_plane_update(state, crtc);
> > >  
> > >  		if (new_crtc_state->update_pipe)
> > >  			intel_encoders_update_pipe(state, crtc);
> > > @@ -14460,7 +14452,7 @@ static void
> > > intel_trans_port_sync_modeset_disables(struct intel_atomic_state
> > > *st
> > >  		!old_slave_crtc_state);
> > >  
> > >  	/* Disable Slave first */
> > > -	intel_pre_plane_update(old_slave_crtc_state,
> > > new_slave_crtc_state);
> > > +	intel_pre_plane_update(state, slave_crtc);
> > >  	if (old_slave_crtc_state->hw.active)
> > >  		intel_old_crtc_state_disables(state,
> > >  					      old_slave_crtc_state,
> > > @@ -14468,7 +14460,7 @@ static void
> > > intel_trans_port_sync_modeset_disables(struct intel_atomic_state
> > > *st
> > >  					      slave_crtc);
> > >  
> > >  	/* Disable Master */
> > > -	intel_pre_plane_update(old_crtc_state, new_crtc_state);
> > > +	intel_pre_plane_update(state, crtc);
> > >  	if (old_crtc_state->hw.active)
> > >  		intel_old_crtc_state_disables(state,
> > >  					      old_crtc_state,
> > > @@ -14508,7 +14500,7 @@ static void
> > > intel_commit_modeset_disables(struct intel_atomic_state *state)
> > >  			else
> > >  				continue;
> > >  		} else {
> > > -			intel_pre_plane_update(old_crtc_state,
> > > new_crtc_state);
> > > +			intel_pre_plane_update(state, crtc);
> > >  
> > >  			if (old_crtc_state->hw.active)
> > >  				intel_old_crtc_state_disables(state,
> > > @@ -14896,7 +14888,7 @@ static void
> > > intel_atomic_commit_tail(struct
> > > intel_atomic_state *state)
> > >  	}
> > >  
> > >  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state, new_crtc_state, i) {
> > > -		intel_post_plane_update(old_crtc_state);
> > > +		intel_post_plane_update(state, crtc);
> > >  
> > >  		if (put_domains[i])
> > >  			modeset_put_power_domains(dev_priv,
> > > put_domains[i]);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 92c7eb243559..70c56abe1a83 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -420,7 +420,7 @@ static void intel_fbc_deactivate(struct
> > > drm_i915_private *dev_priv,
> > >  }
> > >  
> > >  static bool multiple_pipes_ok(struct intel_crtc *crtc,
> > > -			      struct intel_plane_state *plane_state)
> > > +			      const struct intel_plane_state
> > > *plane_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > > @@ -656,8 +656,8 @@ static bool
> > > intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
> > >  }
> > >  
> > >  static void intel_fbc_update_state_cache(struct intel_crtc
> > > *crtc,
> > > -					 struct intel_crtc_state
> > > *crtc_state,
> > > -					 struct intel_plane_state
> > > *plane_state)
> > > +					 const struct intel_crtc_state
> > > *crtc_state,
> > > +					 const struct intel_plane_state
> > > *plane_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > > @@ -855,8 +855,8 @@ static void intel_fbc_get_reg_params(struct
> > > intel_crtc *crtc,
> > >  }
> > >  
> > >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > > -			  struct intel_crtc_state *crtc_state,
> > > -			  struct intel_plane_state *plane_state)
> > > +			  const struct intel_crtc_state *crtc_state,
> > > +			  const struct intel_plane_state *plane_state)
> > 
> > Nice
> > 
> > Other than the first comment, LGTM.
> > 
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > > @@ -1081,8 +1081,8 @@ void intel_fbc_choose_crtc(struct
> > > drm_i915_private *dev_priv,
> > >   * intel_fbc_disable in the middle, as long as it is
> > > deactivated.
> > >   */
> > >  void intel_fbc_enable(struct intel_crtc *crtc,
> > > -		      struct intel_crtc_state *crtc_state,
> > > -		      struct intel_plane_state *plane_state)
> > > +		      const struct intel_crtc_state *crtc_state,
> > > +		      const struct intel_plane_state *plane_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > index 50272eda8d43..f58b0b1e3c5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > @@ -20,14 +20,14 @@ void intel_fbc_choose_crtc(struct
> > > drm_i915_private *dev_priv,
> > >  			   struct intel_atomic_state *state);
> > >  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> > >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> > > -			  struct intel_crtc_state *crtc_state,
> > > -			  struct intel_plane_state *plane_state);
> > > +			  const struct intel_crtc_state *crtc_state,
> > > +			  const struct intel_plane_state *plane_state);
> > >  void intel_fbc_post_update(struct intel_crtc *crtc);
> > >  void intel_fbc_init(struct drm_i915_private *dev_priv);
> > >  void intel_fbc_init_pipe_state(struct drm_i915_private
> > > *dev_priv);
> > >  void intel_fbc_enable(struct intel_crtc *crtc,
> > > -		      struct intel_crtc_state *crtc_state,
> > > -		      struct intel_plane_state *plane_state);
> > > +		      const struct intel_crtc_state *crtc_state,
> > > +		      const struct intel_plane_state *plane_state);
> > >  void intel_fbc_disable(struct intel_crtc *crtc);
> > >  void intel_fbc_global_disable(struct drm_i915_private
> > > *dev_priv);
> > >  void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Clean up intel_{pre, post}_plane_update()

[Ville Syrjälä]

On Tue, Dec 03, 2019 at 09:44:42PM +0000, Souza, Jose wrote:
> On Thu, 2019-11-28 at 14:02 +0200, Ville Syrjälä wrote:
> > On Wed, Nov 27, 2019 at 11:25:07PM +0000, Souza, Jose wrote:
> > > On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Change the calling convention to just pass the state+crtc and
> > > > switch to intel_ types throughout.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 88 +++++++++-----
> > > > ----
> > > > --
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c     | 14 ++--
> > > >  drivers/gpu/drm/i915/display/intel_fbc.h     |  8 +-
> > > >  3 files changed, 51 insertions(+), 59 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index e341b97b7dec..72655b5b1365 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -5920,13 +5920,10 @@ static void
> > > > intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
> > > >   * completely hide the primary plane.
> > > >   */
> > > >  static void
> > > > -intel_post_enable_primary(struct drm_crtc *crtc,
> > > > -			  const struct intel_crtc_state
> > > > *new_crtc_state)
> > > > +intel_post_enable_primary(struct intel_crtc *crtc)
> > > >  {
> > > > -	struct drm_device *dev = crtc->dev;
> > > > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > > > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > > -	enum pipe pipe = intel_crtc->pipe;
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > +	enum pipe pipe = crtc->pipe;
> > > >  
> > > >  	/*
> > > >  	 * Gen2 reports pipe underruns whenever all planes are
> > > > disabled.
> > > > @@ -6062,20 +6059,21 @@ static bool needs_scalerclk_wa(const
> > > > struct
> > > > intel_crtc_state *crtc_state)
> > > >  	return false;
> > > >  }
> > > >  
> > > > -static void intel_post_plane_update(struct intel_crtc_state
> > > > *old_crtc_state)
> > > > +static void intel_post_plane_update(struct intel_atomic_state
> > > > *state,
> > > > +				    struct intel_crtc *crtc)
> > > >  {
> > > > -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > > > uapi.crtc);
> > > > -	struct drm_device *dev = crtc->base.dev;
> > > > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > > > -	struct drm_atomic_state *state = old_crtc_state->uapi.state;
> > > > -	struct intel_crtc_state *new_crtc_state =
> > > > -		intel_atomic_get_new_crtc_state(to_intel_atomic_state(s
> > > > tate),
> > > > -						crtc);
> > > > -	struct drm_plane *primary = crtc->base.primary;
> > > > -	struct drm_plane_state *old_primary_state =
> > > > -		drm_atomic_get_old_plane_state(state, primary);
> > > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > +	struct intel_plane *primary = to_intel_plane(crtc-
> > > > > base.primary);
> > > > +	const struct intel_crtc_state *old_crtc_state =
> > > > +		intel_atomic_get_old_crtc_state(state, crtc);
> > > > +	const struct intel_crtc_state *new_crtc_state =
> > > > +		intel_atomic_get_new_crtc_state(state, crtc);
> > > > +	const struct intel_plane_state *old_primary_state =
> > > > +		intel_atomic_get_old_plane_state(state, primary);
> > > > +	const struct intel_plane_state *new_primary_state =
> > > > +		intel_atomic_get_new_plane_state(state, primary);
> > > >  
> > > > -	intel_frontbuffer_flip(to_i915(crtc->base.dev), new_crtc_state-
> > > > > fb_bits);
> > > > +	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
> > > >  
> > > >  	if (new_crtc_state->update_wm_post && new_crtc_state-
> > > > > hw.active)
> > > >  		intel_update_watermarks(crtc);
> > > > @@ -6083,16 +6081,13 @@ static void
> > > > intel_post_plane_update(struct
> > > > intel_crtc_state *old_crtc_state)
> > > >  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> > > >  		hsw_enable_ips(new_crtc_state);
> > > >  
> > > > -	if (old_primary_state) {
> > > > -		struct drm_plane_state *new_primary_state =
> > > > -			drm_atomic_get_new_plane_state(state, primary);
> > > > -
> > > > +	if (new_primary_state) {
> > > 
> > > This change from old_primary_state to new_primary_state is way more
> > > than the commit message says, the change looks right to me but
> > > maybe it
> > > deserves a separated patch? Same for the same change in
> > > intel_pre_plane_update()
> > 
> > I wanted to change it so I can eliminate old_primary_state in
> > a subsequent patch. For whatever reason that change slipped
> > into this patch. It's a nop change though since
> > !new_state == !old_state always.
> 
> Maybe worthy to mention it in the description?! Will leave that up to
> you.

Sure. Amended a bit while pushing. Thanks for the review.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 5/7] drm/i915: Clean up the gen2 "no planes -> underrun" workaround

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have the active_planes bitmask now so use it to properly
determine when some planes are visible for the gen2 underrun
workaround.

This let's us almost eliminate intel_post_enable_primary().
The manual underrun checks we can simply move into
intel_atomic_commit_tail() since they loop over all the pipes
already. No point in repeating the checks multiple times when
there are multiple pipes in the commit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 155 +++++++++----------
 1 file changed, 70 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 72655b5b1365..5368f3ab70af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5908,37 +5908,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
 	 */
 }
 
-/**
- * intel_post_enable_primary - Perform operations after enabling primary plane
- * @crtc: the CRTC whose primary plane was just enabled
- * @new_crtc_state: the enabling state
- *
- * Performs potentially sleeping operations that must be done after the primary
- * plane is enabled, such as updating FBC and IPS.  Note that this may be
- * called due to an explicit primary plane update, or due to an implicit
- * re-enable that is caused when a sprite plane is updated to no longer
- * completely hide the primary plane.
- */
-static void
-intel_post_enable_primary(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	/*
-	 * Gen2 reports pipe underruns whenever all planes are disabled.
-	 * So don't enable underrun reporting before at least some planes
-	 * are enabled.
-	 * FIXME: Need to fix the logic to work when we turn off all planes
-	 * but leave the pipe running.
-	 */
-	if (IS_GEN(dev_priv, 2))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
-	/* Underruns don't always raise interrupts, so check manually. */
-	intel_check_cpu_fifo_underruns(dev_priv);
-	intel_check_pch_fifo_underruns(dev_priv);
-}
 
 /* FIXME get rid of this and use pre_plane_update */
 static void
@@ -6059,6 +6028,20 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
+static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
+			    const struct intel_crtc_state *new_crtc_state)
+{
+	return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
+		new_crtc_state->active_planes;
+}
+
+static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
+			     const struct intel_crtc_state *new_crtc_state)
+{
+	return old_crtc_state->active_planes &&
+		(!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
+}
+
 static void intel_post_plane_update(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
@@ -6068,10 +6051,9 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *old_primary_state =
-		intel_atomic_get_old_plane_state(state, primary);
 	const struct intel_plane_state *new_primary_state =
 		intel_atomic_get_new_plane_state(state, primary);
+	enum pipe pipe = crtc->pipe;
 
 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 
@@ -6081,22 +6063,16 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
 
-	if (new_primary_state) {
+	if (new_primary_state)
 		intel_fbc_post_update(crtc);
 
-		if (new_primary_state->uapi.visible &&
-		    (needs_modeset(new_crtc_state) ||
-		     !old_primary_state->uapi.visible))
-			intel_post_enable_primary(crtc);
-	}
-
 	if (needs_nv12_wa(old_crtc_state) &&
 	    !needs_nv12_wa(new_crtc_state))
-		skl_wa_827(dev_priv, crtc->pipe, false);
+		skl_wa_827(dev_priv, pipe, false);
 
 	if (needs_scalerclk_wa(old_crtc_state) &&
 	    !needs_scalerclk_wa(new_crtc_state))
-		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
+		icl_wa_scalerclkgating(dev_priv, pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -6108,35 +6084,25 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *old_primary_state =
-		intel_atomic_get_old_plane_state(state, primary);
 	const struct intel_plane_state *new_primary_state =
 		intel_atomic_get_new_plane_state(state, primary);
-	bool modeset = needs_modeset(new_crtc_state);
+	enum pipe pipe = crtc->pipe;
 
 	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
-	if (new_primary_state) {
+	if (new_primary_state)
 		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
-		/*
-		 * Gen2 reports pipe underruns whenever all planes are disabled.
-		 * So disable underrun reporting before all the planes get disabled.
-		 */
-		if (IS_GEN(dev_priv, 2) && old_primary_state->uapi.visible &&
-		    (modeset || !new_primary_state->uapi.visible))
-			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
-	}
 
 	/* Display WA 827 */
 	if (!needs_nv12_wa(old_crtc_state) &&
 	    needs_nv12_wa(new_crtc_state))
-		skl_wa_827(dev_priv, crtc->pipe, true);
+		skl_wa_827(dev_priv, pipe, true);
 
 	/* Wa_2006604312:icl */
 	if (!needs_scalerclk_wa(old_crtc_state) &&
 	    needs_scalerclk_wa(new_crtc_state))
-		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
+		icl_wa_scalerclkgating(dev_priv, pipe, true);
 
 	/*
 	 * Vblank time updates from the shadow to live plane control register
@@ -6149,7 +6115,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
-		intel_wait_for_vblank(dev_priv, crtc->pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
 
 	/*
 	 * IVB workaround: must disable low power watermarks for at least
@@ -6160,33 +6126,43 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (old_crtc_state->hw.active &&
 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
-		intel_wait_for_vblank(dev_priv, crtc->pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
 
 	/*
-	 * If we're doing a modeset, we're done.  No need to do any pre-vblank
-	 * watermark programming here.
+	 * If we're doing a modeset we don't need to do any
+	 * pre-vblank watermark programming here.
 	 */
-	if (needs_modeset(new_crtc_state))
-		return;
+	if (!needs_modeset(new_crtc_state)) {
+		/*
+		 * For platforms that support atomic watermarks, program the
+		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
+		 * will be the intermediate values that are safe for both pre- and
+		 * post- vblank; when vblank happens, the 'active' values will be set
+		 * to the final 'target' values and we'll do this again to get the
+		 * optimal watermarks.  For gen9+ platforms, the values we program here
+		 * will be the final target values which will get automatically latched
+		 * at vblank time; no further programming will be necessary.
+		 *
+		 * If a platform hasn't been transitioned to atomic watermarks yet,
+		 * we'll continue to update watermarks the old way, if flags tell
+		 * us to.
+		 */
+		if (dev_priv->display.initial_watermarks)
+			dev_priv->display.initial_watermarks(state, crtc);
+		else if (new_crtc_state->update_wm_pre)
+			intel_update_watermarks(crtc);
+	}
 
 	/*
-	 * For platforms that support atomic watermarks, program the
-	 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
-	 * will be the intermediate values that are safe for both pre- and
-	 * post- vblank; when vblank happens, the 'active' values will be set
-	 * to the final 'target' values and we'll do this again to get the
-	 * optimal watermarks.  For gen9+ platforms, the values we program here
-	 * will be the final target values which will get automatically latched
-	 * at vblank time; no further programming will be necessary.
+	 * Gen2 reports pipe underruns whenever all planes are disabled.
+	 * So disable underrun reporting before all the planes get disabled.
 	 *
-	 * If a platform hasn't been transitioned to atomic watermarks yet,
-	 * we'll continue to update watermarks the old way, if flags tell
-	 * us to.
+	 * We do this after .initial_watermarks() so that we have a
+	 * chance of catching underruns with the intermediate watermarks
+	 * vs. the old plane configuration.
 	 */
-	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
-	else if (new_crtc_state->update_wm_pre)
-		intel_update_watermarks(crtc);
+	if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 }
 
 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
@@ -14423,13 +14399,6 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	intel_fbc_disable(crtc);
 	intel_disable_shared_dpll(old_crtc_state);
 
-	/*
-	 * Underruns don't always raise interrupts,
-	 * so check manually.
-	 */
-	intel_check_cpu_fifo_underruns(dev_priv);
-	intel_check_pch_fifo_underruns(dev_priv);
-
 	/* FIXME unify this for all platforms */
 	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
@@ -14882,7 +14851,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	 *
 	 * TODO: Move this (and other cleanup) to an async worker eventually.
 	 */
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		/*
+		 * Gen2 reports pipe underruns whenever all planes are disabled.
+		 * So re-enable underrun reporting after some planes get enabled.
+		 *
+		 * We do this before .optimize_watermarks() so that we have a
+		 * chance of catching underruns with the intermediate watermarks
+		 * vs. the new plane configuration.
+		 */
+		if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
+			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+
 		if (dev_priv->display.optimize_watermarks)
 			dev_priv->display.optimize_watermarks(state, crtc);
 	}
@@ -14896,6 +14877,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
 	}
 
+	/* Underruns don't always raise interrupts, so check manually */
+	intel_check_cpu_fifo_underruns(dev_priv);
+	intel_check_pch_fifo_underruns(dev_priv);
+
 	if (state->modeset)
 		intel_verify_planes(state);
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 5/7] drm/i915: Clean up the gen2 "no planes -> underrun" workaround

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have the active_planes bitmask now so use it to properly
determine when some planes are visible for the gen2 underrun
workaround.

This let's us almost eliminate intel_post_enable_primary().
The manual underrun checks we can simply move into
intel_atomic_commit_tail() since they loop over all the pipes
already. No point in repeating the checks multiple times when
there are multiple pipes in the commit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 155 +++++++++----------
 1 file changed, 70 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 72655b5b1365..5368f3ab70af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5908,37 +5908,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
 	 */
 }
 
-/**
- * intel_post_enable_primary - Perform operations after enabling primary plane
- * @crtc: the CRTC whose primary plane was just enabled
- * @new_crtc_state: the enabling state
- *
- * Performs potentially sleeping operations that must be done after the primary
- * plane is enabled, such as updating FBC and IPS.  Note that this may be
- * called due to an explicit primary plane update, or due to an implicit
- * re-enable that is caused when a sprite plane is updated to no longer
- * completely hide the primary plane.
- */
-static void
-intel_post_enable_primary(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	/*
-	 * Gen2 reports pipe underruns whenever all planes are disabled.
-	 * So don't enable underrun reporting before at least some planes
-	 * are enabled.
-	 * FIXME: Need to fix the logic to work when we turn off all planes
-	 * but leave the pipe running.
-	 */
-	if (IS_GEN(dev_priv, 2))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
-	/* Underruns don't always raise interrupts, so check manually. */
-	intel_check_cpu_fifo_underruns(dev_priv);
-	intel_check_pch_fifo_underruns(dev_priv);
-}
 
 /* FIXME get rid of this and use pre_plane_update */
 static void
@@ -6059,6 +6028,20 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
+static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
+			    const struct intel_crtc_state *new_crtc_state)
+{
+	return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
+		new_crtc_state->active_planes;
+}
+
+static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
+			     const struct intel_crtc_state *new_crtc_state)
+{
+	return old_crtc_state->active_planes &&
+		(!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
+}
+
 static void intel_post_plane_update(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
@@ -6068,10 +6051,9 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *old_primary_state =
-		intel_atomic_get_old_plane_state(state, primary);
 	const struct intel_plane_state *new_primary_state =
 		intel_atomic_get_new_plane_state(state, primary);
+	enum pipe pipe = crtc->pipe;
 
 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 
@@ -6081,22 +6063,16 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
 
-	if (new_primary_state) {
+	if (new_primary_state)
 		intel_fbc_post_update(crtc);
 
-		if (new_primary_state->uapi.visible &&
-		    (needs_modeset(new_crtc_state) ||
-		     !old_primary_state->uapi.visible))
-			intel_post_enable_primary(crtc);
-	}
-
 	if (needs_nv12_wa(old_crtc_state) &&
 	    !needs_nv12_wa(new_crtc_state))
-		skl_wa_827(dev_priv, crtc->pipe, false);
+		skl_wa_827(dev_priv, pipe, false);
 
 	if (needs_scalerclk_wa(old_crtc_state) &&
 	    !needs_scalerclk_wa(new_crtc_state))
-		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
+		icl_wa_scalerclkgating(dev_priv, pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -6108,35 +6084,25 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *old_primary_state =
-		intel_atomic_get_old_plane_state(state, primary);
 	const struct intel_plane_state *new_primary_state =
 		intel_atomic_get_new_plane_state(state, primary);
-	bool modeset = needs_modeset(new_crtc_state);
+	enum pipe pipe = crtc->pipe;
 
 	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
 		hsw_disable_ips(old_crtc_state);
 
-	if (new_primary_state) {
+	if (new_primary_state)
 		intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
-		/*
-		 * Gen2 reports pipe underruns whenever all planes are disabled.
-		 * So disable underrun reporting before all the planes get disabled.
-		 */
-		if (IS_GEN(dev_priv, 2) && old_primary_state->uapi.visible &&
-		    (modeset || !new_primary_state->uapi.visible))
-			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
-	}
 
 	/* Display WA 827 */
 	if (!needs_nv12_wa(old_crtc_state) &&
 	    needs_nv12_wa(new_crtc_state))
-		skl_wa_827(dev_priv, crtc->pipe, true);
+		skl_wa_827(dev_priv, pipe, true);
 
 	/* Wa_2006604312:icl */
 	if (!needs_scalerclk_wa(old_crtc_state) &&
 	    needs_scalerclk_wa(new_crtc_state))
-		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
+		icl_wa_scalerclkgating(dev_priv, pipe, true);
 
 	/*
 	 * Vblank time updates from the shadow to live plane control register
@@ -6149,7 +6115,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
-		intel_wait_for_vblank(dev_priv, crtc->pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
 
 	/*
 	 * IVB workaround: must disable low power watermarks for at least
@@ -6160,33 +6126,43 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (old_crtc_state->hw.active &&
 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
-		intel_wait_for_vblank(dev_priv, crtc->pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
 
 	/*
-	 * If we're doing a modeset, we're done.  No need to do any pre-vblank
-	 * watermark programming here.
+	 * If we're doing a modeset we don't need to do any
+	 * pre-vblank watermark programming here.
 	 */
-	if (needs_modeset(new_crtc_state))
-		return;
+	if (!needs_modeset(new_crtc_state)) {
+		/*
+		 * For platforms that support atomic watermarks, program the
+		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
+		 * will be the intermediate values that are safe for both pre- and
+		 * post- vblank; when vblank happens, the 'active' values will be set
+		 * to the final 'target' values and we'll do this again to get the
+		 * optimal watermarks.  For gen9+ platforms, the values we program here
+		 * will be the final target values which will get automatically latched
+		 * at vblank time; no further programming will be necessary.
+		 *
+		 * If a platform hasn't been transitioned to atomic watermarks yet,
+		 * we'll continue to update watermarks the old way, if flags tell
+		 * us to.
+		 */
+		if (dev_priv->display.initial_watermarks)
+			dev_priv->display.initial_watermarks(state, crtc);
+		else if (new_crtc_state->update_wm_pre)
+			intel_update_watermarks(crtc);
+	}
 
 	/*
-	 * For platforms that support atomic watermarks, program the
-	 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
-	 * will be the intermediate values that are safe for both pre- and
-	 * post- vblank; when vblank happens, the 'active' values will be set
-	 * to the final 'target' values and we'll do this again to get the
-	 * optimal watermarks.  For gen9+ platforms, the values we program here
-	 * will be the final target values which will get automatically latched
-	 * at vblank time; no further programming will be necessary.
+	 * Gen2 reports pipe underruns whenever all planes are disabled.
+	 * So disable underrun reporting before all the planes get disabled.
 	 *
-	 * If a platform hasn't been transitioned to atomic watermarks yet,
-	 * we'll continue to update watermarks the old way, if flags tell
-	 * us to.
+	 * We do this after .initial_watermarks() so that we have a
+	 * chance of catching underruns with the intermediate watermarks
+	 * vs. the old plane configuration.
 	 */
-	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
-	else if (new_crtc_state->update_wm_pre)
-		intel_update_watermarks(crtc);
+	if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 }
 
 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
@@ -14423,13 +14399,6 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	intel_fbc_disable(crtc);
 	intel_disable_shared_dpll(old_crtc_state);
 
-	/*
-	 * Underruns don't always raise interrupts,
-	 * so check manually.
-	 */
-	intel_check_cpu_fifo_underruns(dev_priv);
-	intel_check_pch_fifo_underruns(dev_priv);
-
 	/* FIXME unify this for all platforms */
 	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
@@ -14882,7 +14851,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	 *
 	 * TODO: Move this (and other cleanup) to an async worker eventually.
 	 */
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		/*
+		 * Gen2 reports pipe underruns whenever all planes are disabled.
+		 * So re-enable underrun reporting after some planes get enabled.
+		 *
+		 * We do this before .optimize_watermarks() so that we have a
+		 * chance of catching underruns with the intermediate watermarks
+		 * vs. the new plane configuration.
+		 */
+		if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
+			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+
 		if (dev_priv->display.optimize_watermarks)
 			dev_priv->display.optimize_watermarks(state, crtc);
 	}
@@ -14896,6 +14877,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
 	}
 
+	/* Underruns don't always raise interrupts, so check manually */
+	intel_check_cpu_fifo_underruns(dev_priv);
+	intel_check_pch_fifo_underruns(dev_priv);
+
 	if (state->modeset)
 		intel_verify_planes(state);
 
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/7] drm/i915: Clean up the gen2 "no planes -> underrun" workaround

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have the active_planes bitmask now so use it to properly
> determine when some planes are visible for the gen2 underrun
> workaround.
> 
> This let's us almost eliminate intel_post_enable_primary().
> The manual underrun checks we can simply move into
> intel_atomic_commit_tail() since they loop over all the pipes
> already. No point in repeating the checks multiple times when
> there are multiple pipes in the commit.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 155 +++++++++------
> ----
>  1 file changed, 70 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 72655b5b1365..5368f3ab70af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5908,37 +5908,6 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>  	 */
>  }
>  
> -/**
> - * intel_post_enable_primary - Perform operations after enabling
> primary plane
> - * @crtc: the CRTC whose primary plane was just enabled
> - * @new_crtc_state: the enabling state
> - *
> - * Performs potentially sleeping operations that must be done after
> the primary
> - * plane is enabled, such as updating FBC and IPS.  Note that this
> may be
> - * called due to an explicit primary plane update, or due to an
> implicit
> - * re-enable that is caused when a sprite plane is updated to no
> longer
> - * completely hide the primary plane.
> - */
> -static void
> -intel_post_enable_primary(struct intel_crtc *crtc)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum pipe pipe = crtc->pipe;
> -
> -	/*
> -	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -	 * So don't enable underrun reporting before at least some
> planes
> -	 * are enabled.
> -	 * FIXME: Need to fix the logic to work when we turn off all
> planes
> -	 * but leave the pipe running.
> -	 */
> -	if (IS_GEN(dev_priv, 2))
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> true);
> -
> -	/* Underruns don't always raise interrupts, so check manually.
> */
> -	intel_check_cpu_fifo_underruns(dev_priv);
> -	intel_check_pch_fifo_underruns(dev_priv);
> -}
>  
>  /* FIXME get rid of this and use pre_plane_update */
>  static void
> @@ -6059,6 +6028,20 @@ static bool needs_scalerclk_wa(const struct
> intel_crtc_state *crtc_state)
>  	return false;
>  }
>  
> +static bool planes_enabling(const struct intel_crtc_state
> *old_crtc_state,
> +			    const struct intel_crtc_state
> *new_crtc_state)
> +{
> +	return (!old_crtc_state->active_planes ||
> needs_modeset(new_crtc_state)) &&
> +		new_crtc_state->active_planes;
> +}
> +
> +static bool planes_disabling(const struct intel_crtc_state
> *old_crtc_state,
> +			     const struct intel_crtc_state
> *new_crtc_state)
> +{
> +	return old_crtc_state->active_planes &&
> +		(!new_crtc_state->active_planes ||
> needs_modeset(new_crtc_state));
> +}
> +
>  static void intel_post_plane_update(struct intel_atomic_state
> *state,
>  				    struct intel_crtc *crtc)
>  {
> @@ -6068,10 +6051,9 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *old_primary_state =
> -		intel_atomic_get_old_plane_state(state, primary);
>  	const struct intel_plane_state *new_primary_state =
>  		intel_atomic_get_new_plane_state(state, primary);
> +	enum pipe pipe = crtc->pipe;
>  
>  	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
> @@ -6081,22 +6063,16 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>  		hsw_enable_ips(new_crtc_state);
>  
> -	if (new_primary_state) {
> +	if (new_primary_state)
>  		intel_fbc_post_update(crtc);
>  
> -		if (new_primary_state->uapi.visible &&
> -		    (needs_modeset(new_crtc_state) ||
> -		     !old_primary_state->uapi.visible))
> -			intel_post_enable_primary(crtc);
> -	}
> -
>  	if (needs_nv12_wa(old_crtc_state) &&
>  	    !needs_nv12_wa(new_crtc_state))
> -		skl_wa_827(dev_priv, crtc->pipe, false);
> +		skl_wa_827(dev_priv, pipe, false);

Nitpick: could be left as it was(s/crtc->pipe/pipe)

>  
>  	if (needs_scalerclk_wa(old_crtc_state) &&
>  	    !needs_scalerclk_wa(new_crtc_state))
> -		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> +		icl_wa_scalerclkgating(dev_priv, pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_atomic_state *state,
> @@ -6108,35 +6084,25 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *old_primary_state =
> -		intel_atomic_get_old_plane_state(state, primary);
>  	const struct intel_plane_state *new_primary_state =
>  		intel_atomic_get_new_plane_state(state, primary);
> -	bool modeset = needs_modeset(new_crtc_state);
> +	enum pipe pipe = crtc->pipe;
>  
>  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
> -	if (new_primary_state) {
> +	if (new_primary_state)
>  		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
> -		/*
> -		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -		 * So disable underrun reporting before all the planes
> get disabled.
> -		 */
> -		if (IS_GEN(dev_priv, 2) && old_primary_state-
> >uapi.visible &&
> -		    (modeset || !new_primary_state->uapi.visible))
> -			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, false);
> -	}
>  
>  	/* Display WA 827 */
>  	if (!needs_nv12_wa(old_crtc_state) &&
>  	    needs_nv12_wa(new_crtc_state))
> -		skl_wa_827(dev_priv, crtc->pipe, true);
> +		skl_wa_827(dev_priv, pipe, true);
>  
>  	/* Wa_2006604312:icl */
>  	if (!needs_scalerclk_wa(old_crtc_state) &&
>  	    needs_scalerclk_wa(new_crtc_state))
> -		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> +		icl_wa_scalerclkgating(dev_priv, pipe, true);
>  
>  	/*
>  	 * Vblank time updates from the shadow to live plane control
> register
> @@ -6149,7 +6115,7 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  	 */
>  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
> -		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +		intel_wait_for_vblank(dev_priv, pipe);
>  
>  	/*
>  	 * IVB workaround: must disable low power watermarks for at
> least
> @@ -6160,33 +6126,43 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  	 */
>  	if (old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_lp_wm &&
> ilk_disable_lp_wm(dev_priv))
> -		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +		intel_wait_for_vblank(dev_priv, pipe);
>  
>  	/*
> -	 * If we're doing a modeset, we're done.  No need to do any
> pre-vblank
> -	 * watermark programming here.
> +	 * If we're doing a modeset we don't need to do any
> +	 * pre-vblank watermark programming here.
>  	 */
> -	if (needs_modeset(new_crtc_state))
> -		return;
> +	if (!needs_modeset(new_crtc_state)) {
> +		/*
> +		 * For platforms that support atomic watermarks,
> program the
> +		 * 'intermediate' watermarks immediately.  On pre-gen9
> platforms, these
> +		 * will be the intermediate values that are safe for
> both pre- and
> +		 * post- vblank; when vblank happens, the 'active'
> values will be set
> +		 * to the final 'target' values and we'll do this again
> to get the
> +		 * optimal watermarks.  For gen9+ platforms, the values
> we program here
> +		 * will be the final target values which will get
> automatically latched
> +		 * at vblank time; no further programming will be
> necessary.
> +		 *
> +		 * If a platform hasn't been transitioned to atomic
> watermarks yet,
> +		 * we'll continue to update watermarks the old way, if
> flags tell
> +		 * us to.
> +		 */

A few lines are now over 80 characters but I know you did not wanted to
change it.


Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +		if (dev_priv->display.initial_watermarks)
> +			dev_priv->display.initial_watermarks(state,
> crtc);
> +		else if (new_crtc_state->update_wm_pre)
> +			intel_update_watermarks(crtc);
> +	}
>  
>  	/*
> -	 * For platforms that support atomic watermarks, program the
> -	 * 'intermediate' watermarks immediately.  On pre-gen9
> platforms, these
> -	 * will be the intermediate values that are safe for both pre-
> and
> -	 * post- vblank; when vblank happens, the 'active' values will
> be set
> -	 * to the final 'target' values and we'll do this again to get
> the
> -	 * optimal watermarks.  For gen9+ platforms, the values we
> program here
> -	 * will be the final target values which will get automatically
> latched
> -	 * at vblank time; no further programming will be necessary.
> +	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +	 * So disable underrun reporting before all the planes get
> disabled.
>  	 *
> -	 * If a platform hasn't been transitioned to atomic watermarks
> yet,
> -	 * we'll continue to update watermarks the old way, if flags
> tell
> -	 * us to.
> +	 * We do this after .initial_watermarks() so that we have a
> +	 * chance of catching underruns with the intermediate
> watermarks
> +	 * vs. the old plane configuration.
>  	 */
> -	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> -	else if (new_crtc_state->update_wm_pre)
> -		intel_update_watermarks(crtc);
> +	if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state,
> new_crtc_state))
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
>  }
>  
>  static void intel_crtc_disable_planes(struct intel_atomic_state
> *state,
> @@ -14423,13 +14399,6 @@ static void
> intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	intel_fbc_disable(crtc);
>  	intel_disable_shared_dpll(old_crtc_state);
>  
> -	/*
> -	 * Underruns don't always raise interrupts,
> -	 * so check manually.
> -	 */
> -	intel_check_cpu_fifo_underruns(dev_priv);
> -	intel_check_pch_fifo_underruns(dev_priv);
> -
>  	/* FIXME unify this for all platforms */
>  	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
> @@ -14882,7 +14851,19 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	 *
>  	 * TODO: Move this (and other cleanup) to an async worker
> eventually.
>  	 */
> -	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> i) {
> +	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> +					    new_crtc_state, i) {
> +		/*
> +		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +		 * So re-enable underrun reporting after some planes
> get enabled.
> +		 *
> +		 * We do this before .optimize_watermarks() so that we
> have a
> +		 * chance of catching underruns with the intermediate
> watermarks
> +		 * vs. the new plane configuration.
> +		 */
> +		if (IS_GEN(dev_priv, 2) &&
> planes_enabling(old_crtc_state, new_crtc_state))
> +			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, true);
> +
>  		if (dev_priv->display.optimize_watermarks)
>  			dev_priv->display.optimize_watermarks(state,
> crtc);
>  	}
> @@ -14896,6 +14877,10 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  		intel_modeset_verify_crtc(crtc, state, old_crtc_state,
> new_crtc_state);
>  	}
>  
> +	/* Underruns don't always raise interrupts, so check manually
> */
> +	intel_check_cpu_fifo_underruns(dev_priv);
> +	intel_check_pch_fifo_underruns(dev_priv);
> +
>  	if (state->modeset)
>  		intel_verify_planes(state);
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Clean up the gen2 "no planes -> underrun" workaround

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have the active_planes bitmask now so use it to properly
> determine when some planes are visible for the gen2 underrun
> workaround.
> 
> This let's us almost eliminate intel_post_enable_primary().
> The manual underrun checks we can simply move into
> intel_atomic_commit_tail() since they loop over all the pipes
> already. No point in repeating the checks multiple times when
> there are multiple pipes in the commit.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 155 +++++++++------
> ----
>  1 file changed, 70 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 72655b5b1365..5368f3ab70af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5908,37 +5908,6 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>  	 */
>  }
>  
> -/**
> - * intel_post_enable_primary - Perform operations after enabling
> primary plane
> - * @crtc: the CRTC whose primary plane was just enabled
> - * @new_crtc_state: the enabling state
> - *
> - * Performs potentially sleeping operations that must be done after
> the primary
> - * plane is enabled, such as updating FBC and IPS.  Note that this
> may be
> - * called due to an explicit primary plane update, or due to an
> implicit
> - * re-enable that is caused when a sprite plane is updated to no
> longer
> - * completely hide the primary plane.
> - */
> -static void
> -intel_post_enable_primary(struct intel_crtc *crtc)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum pipe pipe = crtc->pipe;
> -
> -	/*
> -	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -	 * So don't enable underrun reporting before at least some
> planes
> -	 * are enabled.
> -	 * FIXME: Need to fix the logic to work when we turn off all
> planes
> -	 * but leave the pipe running.
> -	 */
> -	if (IS_GEN(dev_priv, 2))
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> true);
> -
> -	/* Underruns don't always raise interrupts, so check manually.
> */
> -	intel_check_cpu_fifo_underruns(dev_priv);
> -	intel_check_pch_fifo_underruns(dev_priv);
> -}
>  
>  /* FIXME get rid of this and use pre_plane_update */
>  static void
> @@ -6059,6 +6028,20 @@ static bool needs_scalerclk_wa(const struct
> intel_crtc_state *crtc_state)
>  	return false;
>  }
>  
> +static bool planes_enabling(const struct intel_crtc_state
> *old_crtc_state,
> +			    const struct intel_crtc_state
> *new_crtc_state)
> +{
> +	return (!old_crtc_state->active_planes ||
> needs_modeset(new_crtc_state)) &&
> +		new_crtc_state->active_planes;
> +}
> +
> +static bool planes_disabling(const struct intel_crtc_state
> *old_crtc_state,
> +			     const struct intel_crtc_state
> *new_crtc_state)
> +{
> +	return old_crtc_state->active_planes &&
> +		(!new_crtc_state->active_planes ||
> needs_modeset(new_crtc_state));
> +}
> +
>  static void intel_post_plane_update(struct intel_atomic_state
> *state,
>  				    struct intel_crtc *crtc)
>  {
> @@ -6068,10 +6051,9 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *old_primary_state =
> -		intel_atomic_get_old_plane_state(state, primary);
>  	const struct intel_plane_state *new_primary_state =
>  		intel_atomic_get_new_plane_state(state, primary);
> +	enum pipe pipe = crtc->pipe;
>  
>  	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
> @@ -6081,22 +6063,16 @@ static void intel_post_plane_update(struct
> intel_atomic_state *state,
>  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>  		hsw_enable_ips(new_crtc_state);
>  
> -	if (new_primary_state) {
> +	if (new_primary_state)
>  		intel_fbc_post_update(crtc);
>  
> -		if (new_primary_state->uapi.visible &&
> -		    (needs_modeset(new_crtc_state) ||
> -		     !old_primary_state->uapi.visible))
> -			intel_post_enable_primary(crtc);
> -	}
> -
>  	if (needs_nv12_wa(old_crtc_state) &&
>  	    !needs_nv12_wa(new_crtc_state))
> -		skl_wa_827(dev_priv, crtc->pipe, false);
> +		skl_wa_827(dev_priv, pipe, false);

Nitpick: could be left as it was(s/crtc->pipe/pipe)

>  
>  	if (needs_scalerclk_wa(old_crtc_state) &&
>  	    !needs_scalerclk_wa(new_crtc_state))
> -		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> +		icl_wa_scalerclkgating(dev_priv, pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_atomic_state *state,
> @@ -6108,35 +6084,25 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *old_primary_state =
> -		intel_atomic_get_old_plane_state(state, primary);
>  	const struct intel_plane_state *new_primary_state =
>  		intel_atomic_get_new_plane_state(state, primary);
> -	bool modeset = needs_modeset(new_crtc_state);
> +	enum pipe pipe = crtc->pipe;
>  
>  	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
>  		hsw_disable_ips(old_crtc_state);
>  
> -	if (new_primary_state) {
> +	if (new_primary_state)
>  		intel_fbc_pre_update(crtc, new_crtc_state,
> new_primary_state);
> -		/*
> -		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -		 * So disable underrun reporting before all the planes
> get disabled.
> -		 */
> -		if (IS_GEN(dev_priv, 2) && old_primary_state-
> >uapi.visible &&
> -		    (modeset || !new_primary_state->uapi.visible))
> -			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, false);
> -	}
>  
>  	/* Display WA 827 */
>  	if (!needs_nv12_wa(old_crtc_state) &&
>  	    needs_nv12_wa(new_crtc_state))
> -		skl_wa_827(dev_priv, crtc->pipe, true);
> +		skl_wa_827(dev_priv, pipe, true);
>  
>  	/* Wa_2006604312:icl */
>  	if (!needs_scalerclk_wa(old_crtc_state) &&
>  	    needs_scalerclk_wa(new_crtc_state))
> -		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> +		icl_wa_scalerclkgating(dev_priv, pipe, true);
>  
>  	/*
>  	 * Vblank time updates from the shadow to live plane control
> register
> @@ -6149,7 +6115,7 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  	 */
>  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_cxsr &&
> intel_set_memory_cxsr(dev_priv, false))
> -		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +		intel_wait_for_vblank(dev_priv, pipe);
>  
>  	/*
>  	 * IVB workaround: must disable low power watermarks for at
> least
> @@ -6160,33 +6126,43 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  	 */
>  	if (old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_lp_wm &&
> ilk_disable_lp_wm(dev_priv))
> -		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +		intel_wait_for_vblank(dev_priv, pipe);
>  
>  	/*
> -	 * If we're doing a modeset, we're done.  No need to do any
> pre-vblank
> -	 * watermark programming here.
> +	 * If we're doing a modeset we don't need to do any
> +	 * pre-vblank watermark programming here.
>  	 */
> -	if (needs_modeset(new_crtc_state))
> -		return;
> +	if (!needs_modeset(new_crtc_state)) {
> +		/*
> +		 * For platforms that support atomic watermarks,
> program the
> +		 * 'intermediate' watermarks immediately.  On pre-gen9
> platforms, these
> +		 * will be the intermediate values that are safe for
> both pre- and
> +		 * post- vblank; when vblank happens, the 'active'
> values will be set
> +		 * to the final 'target' values and we'll do this again
> to get the
> +		 * optimal watermarks.  For gen9+ platforms, the values
> we program here
> +		 * will be the final target values which will get
> automatically latched
> +		 * at vblank time; no further programming will be
> necessary.
> +		 *
> +		 * If a platform hasn't been transitioned to atomic
> watermarks yet,
> +		 * we'll continue to update watermarks the old way, if
> flags tell
> +		 * us to.
> +		 */

A few lines are now over 80 characters but I know you did not wanted to
change it.


Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +		if (dev_priv->display.initial_watermarks)
> +			dev_priv->display.initial_watermarks(state,
> crtc);
> +		else if (new_crtc_state->update_wm_pre)
> +			intel_update_watermarks(crtc);
> +	}
>  
>  	/*
> -	 * For platforms that support atomic watermarks, program the
> -	 * 'intermediate' watermarks immediately.  On pre-gen9
> platforms, these
> -	 * will be the intermediate values that are safe for both pre-
> and
> -	 * post- vblank; when vblank happens, the 'active' values will
> be set
> -	 * to the final 'target' values and we'll do this again to get
> the
> -	 * optimal watermarks.  For gen9+ platforms, the values we
> program here
> -	 * will be the final target values which will get automatically
> latched
> -	 * at vblank time; no further programming will be necessary.
> +	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +	 * So disable underrun reporting before all the planes get
> disabled.
>  	 *
> -	 * If a platform hasn't been transitioned to atomic watermarks
> yet,
> -	 * we'll continue to update watermarks the old way, if flags
> tell
> -	 * us to.
> +	 * We do this after .initial_watermarks() so that we have a
> +	 * chance of catching underruns with the intermediate
> watermarks
> +	 * vs. the old plane configuration.
>  	 */
> -	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> -	else if (new_crtc_state->update_wm_pre)
> -		intel_update_watermarks(crtc);
> +	if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state,
> new_crtc_state))
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
>  }
>  
>  static void intel_crtc_disable_planes(struct intel_atomic_state
> *state,
> @@ -14423,13 +14399,6 @@ static void
> intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	intel_fbc_disable(crtc);
>  	intel_disable_shared_dpll(old_crtc_state);
>  
> -	/*
> -	 * Underruns don't always raise interrupts,
> -	 * so check manually.
> -	 */
> -	intel_check_cpu_fifo_underruns(dev_priv);
> -	intel_check_pch_fifo_underruns(dev_priv);
> -
>  	/* FIXME unify this for all platforms */
>  	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
> @@ -14882,7 +14851,19 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  	 *
>  	 * TODO: Move this (and other cleanup) to an async worker
> eventually.
>  	 */
> -	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> i) {
> +	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> +					    new_crtc_state, i) {
> +		/*
> +		 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +		 * So re-enable underrun reporting after some planes
> get enabled.
> +		 *
> +		 * We do this before .optimize_watermarks() so that we
> have a
> +		 * chance of catching underruns with the intermediate
> watermarks
> +		 * vs. the new plane configuration.
> +		 */
> +		if (IS_GEN(dev_priv, 2) &&
> planes_enabling(old_crtc_state, new_crtc_state))
> +			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, true);
> +
>  		if (dev_priv->display.optimize_watermarks)
>  			dev_priv->display.optimize_watermarks(state,
> crtc);
>  	}
> @@ -14896,6 +14877,10 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  		intel_modeset_verify_crtc(crtc, state, old_crtc_state,
> new_crtc_state);
>  	}
>  
> +	/* Underruns don't always raise interrupts, so check manually
> */
> +	intel_check_cpu_fifo_underruns(dev_priv);
> +	intel_check_pch_fifo_underruns(dev_priv);
> +
>  	if (state->modeset)
>  		intel_verify_planes(state);
>  
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 6/7] drm/i915: Nuke intel_pre_disable_primary_noatomic()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's just inline intel_pre_disable_primary_noatomic() into
intel_plane_disable_noatomic(). The CxSR disable we can do
regardless of which plane we're disabling, and while at it we can
make the gen2 underrun w/a accurate by consulting the active_planes
bitmask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++------------
 1 file changed, 22 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5368f3ab70af..4377ee2eee56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -171,7 +171,6 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 					 struct drm_modeset_acquire_ctx *ctx);
-static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 
 struct intel_limit {
 	struct {
@@ -3212,6 +3211,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 					 struct intel_plane *plane)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		to_intel_crtc_state(crtc->base.state);
 	struct intel_plane_state *plane_state =
@@ -3227,7 +3227,27 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY)
-		intel_pre_disable_primary_noatomic(&crtc->base);
+		hsw_disable_ips(crtc_state);
+
+	/*
+	 * Vblank time updates from the shadow to live plane control register
+	 * are blocked if the memory self-refresh mode is active at that
+	 * moment. So to make sure the plane gets truly disabled, disable
+	 * first the self-refresh mode. The self-refresh enable bit in turn
+	 * will be checked/applied by the HW only at the next frame start
+	 * event which is after the vblank start event, so we need to have a
+	 * wait-for-vblank between disabling the plane and the pipe.
+	 */
+	if (HAS_GMCH(dev_priv) &&
+	    intel_set_memory_cxsr(dev_priv, false))
+		intel_wait_for_vblank(dev_priv, crtc->pipe);
+
+	/*
+	 * Gen2 reports pipe underruns whenever all planes are disabled.
+	 * So disable underrun reporting before all the planes get disabled.
+	 */
+	if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 
 	intel_disable_plane(plane, crtc_state);
 }
@@ -5908,39 +5928,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
 	 */
 }
 
-
-/* FIXME get rid of this and use pre_plane_update */
-static void
-intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
-
-	/*
-	 * Gen2 reports pipe underruns whenever all planes are disabled.
-	 * So disable underrun reporting before all the planes get disabled.
-	 */
-	if (IS_GEN(dev_priv, 2))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
-	hsw_disable_ips(to_intel_crtc_state(crtc->state));
-
-	/*
-	 * Vblank time updates from the shadow to live plane control register
-	 * are blocked if the memory self-refresh mode is active at that
-	 * moment. So to make sure the plane gets truly disabled, disable
-	 * first the self-refresh mode. The self-refresh enable bit in turn
-	 * will be checked/applied by the HW only at the next frame start
-	 * event which is after the vblank start event, so we need to have a
-	 * wait-for-vblank between disabling the plane and the pipe.
-	 */
-	if (HAS_GMCH(dev_priv) &&
-	    intel_set_memory_cxsr(dev_priv, false))
-		intel_wait_for_vblank(dev_priv, pipe);
-}
-
 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 6/7] drm/i915: Nuke intel_pre_disable_primary_noatomic()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's just inline intel_pre_disable_primary_noatomic() into
intel_plane_disable_noatomic(). The CxSR disable we can do
regardless of which plane we're disabling, and while at it we can
make the gen2 underrun w/a accurate by consulting the active_planes
bitmask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++------------
 1 file changed, 22 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5368f3ab70af..4377ee2eee56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -171,7 +171,6 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 					 struct drm_modeset_acquire_ctx *ctx);
-static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 
 struct intel_limit {
 	struct {
@@ -3212,6 +3211,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 					 struct intel_plane *plane)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		to_intel_crtc_state(crtc->base.state);
 	struct intel_plane_state *plane_state =
@@ -3227,7 +3227,27 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY)
-		intel_pre_disable_primary_noatomic(&crtc->base);
+		hsw_disable_ips(crtc_state);
+
+	/*
+	 * Vblank time updates from the shadow to live plane control register
+	 * are blocked if the memory self-refresh mode is active at that
+	 * moment. So to make sure the plane gets truly disabled, disable
+	 * first the self-refresh mode. The self-refresh enable bit in turn
+	 * will be checked/applied by the HW only at the next frame start
+	 * event which is after the vblank start event, so we need to have a
+	 * wait-for-vblank between disabling the plane and the pipe.
+	 */
+	if (HAS_GMCH(dev_priv) &&
+	    intel_set_memory_cxsr(dev_priv, false))
+		intel_wait_for_vblank(dev_priv, crtc->pipe);
+
+	/*
+	 * Gen2 reports pipe underruns whenever all planes are disabled.
+	 * So disable underrun reporting before all the planes get disabled.
+	 */
+	if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 
 	intel_disable_plane(plane, crtc_state);
 }
@@ -5908,39 +5928,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
 	 */
 }
 
-
-/* FIXME get rid of this and use pre_plane_update */
-static void
-intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
-
-	/*
-	 * Gen2 reports pipe underruns whenever all planes are disabled.
-	 * So disable underrun reporting before all the planes get disabled.
-	 */
-	if (IS_GEN(dev_priv, 2))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
-	hsw_disable_ips(to_intel_crtc_state(crtc->state));
-
-	/*
-	 * Vblank time updates from the shadow to live plane control register
-	 * are blocked if the memory self-refresh mode is active at that
-	 * moment. So to make sure the plane gets truly disabled, disable
-	 * first the self-refresh mode. The self-refresh enable bit in turn
-	 * will be checked/applied by the HW only at the next frame start
-	 * event which is after the vblank start event, so we need to have a
-	 * wait-for-vblank between disabling the plane and the pipe.
-	 */
-	if (HAS_GMCH(dev_priv) &&
-	    intel_set_memory_cxsr(dev_priv, false))
-		intel_wait_for_vblank(dev_priv, pipe);
-}
-
 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 6/7] drm/i915: Nuke intel_pre_disable_primary_noatomic()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's just inline intel_pre_disable_primary_noatomic() into
> intel_plane_disable_noatomic(). The CxSR disable we can do
> regardless of which plane we're disabling, and while at it we can
> make the gen2 underrun w/a accurate by consulting the active_planes
> bitmask.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++--------
> ----
>  1 file changed, 22 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5368f3ab70af..4377ee2eee56 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -171,7 +171,6 @@ static void ironlake_pfit_disable(const struct
> intel_crtc_state *old_crtc_state)
>  static void ironlake_pfit_enable(const struct intel_crtc_state
> *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>  					 struct drm_modeset_acquire_ctx
> *ctx);
> -static void intel_pre_disable_primary_noatomic(struct drm_crtc
> *crtc);
>  
>  struct intel_limit {
>  	struct {
> @@ -3212,6 +3211,7 @@ static void fixup_active_planes(struct
> intel_crtc_state *crtc_state)
>  static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  					 struct intel_plane *plane)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		to_intel_crtc_state(crtc->base.state);
>  	struct intel_plane_state *plane_state =
> @@ -3227,7 +3227,27 @@ static void
> intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	if (plane->id == PLANE_PRIMARY)
> -		intel_pre_disable_primary_noatomic(&crtc->base);
> +		hsw_disable_ips(crtc_state);
> +
> +	/*
> +	 * Vblank time updates from the shadow to live plane control
> register
> +	 * are blocked if the memory self-refresh mode is active at
> that
> +	 * moment. So to make sure the plane gets truly disabled,
> disable
> +	 * first the self-refresh mode. The self-refresh enable bit in
> turn
> +	 * will be checked/applied by the HW only at the next frame
> start
> +	 * event which is after the vblank start event, so we need to
> have a
> +	 * wait-for-vblank between disabling the plane and the pipe.
> +	 */
> +	if (HAS_GMCH(dev_priv) &&
> +	    intel_set_memory_cxsr(dev_priv, false))
> +		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +
> +	/*
> +	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +	 * So disable underrun reporting before all the planes get
> disabled.
> +	 */
> +	if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc-
> >pipe, false);
>  
>  	intel_disable_plane(plane, crtc_state);
>  }
> @@ -5908,39 +5928,6 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>  	 */
>  }
>  
> -
> -/* FIXME get rid of this and use pre_plane_update */
> -static void
> -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> -
> -	/*
> -	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -	 * So disable underrun reporting before all the planes get
> disabled.
> -	 */
> -	if (IS_GEN(dev_priv, 2))
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
> -
> -	hsw_disable_ips(to_intel_crtc_state(crtc->state));
> -
> -	/*
> -	 * Vblank time updates from the shadow to live plane control
> register
> -	 * are blocked if the memory self-refresh mode is active at
> that
> -	 * moment. So to make sure the plane gets truly disabled,
> disable
> -	 * first the self-refresh mode. The self-refresh enable bit in
> turn
> -	 * will be checked/applied by the HW only at the next frame
> start
> -	 * event which is after the vblank start event, so we need to
> have a
> -	 * wait-for-vblank between disabling the plane and the pipe.
> -	 */
> -	if (HAS_GMCH(dev_priv) &&
> -	    intel_set_memory_cxsr(dev_priv, false))
> -		intel_wait_for_vblank(dev_priv, pipe);
> -}
> -
>  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
> *old_crtc_state,
>  				       const struct intel_crtc_state
> *new_crtc_state)
>  {
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Nuke intel_pre_disable_primary_noatomic()

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's just inline intel_pre_disable_primary_noatomic() into
> intel_plane_disable_noatomic(). The CxSR disable we can do
> regardless of which plane we're disabling, and while at it we can
> make the gen2 underrun w/a accurate by consulting the active_planes
> bitmask.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++--------
> ----
>  1 file changed, 22 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5368f3ab70af..4377ee2eee56 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -171,7 +171,6 @@ static void ironlake_pfit_disable(const struct
> intel_crtc_state *old_crtc_state)
>  static void ironlake_pfit_enable(const struct intel_crtc_state
> *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>  					 struct drm_modeset_acquire_ctx
> *ctx);
> -static void intel_pre_disable_primary_noatomic(struct drm_crtc
> *crtc);
>  
>  struct intel_limit {
>  	struct {
> @@ -3212,6 +3211,7 @@ static void fixup_active_planes(struct
> intel_crtc_state *crtc_state)
>  static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  					 struct intel_plane *plane)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		to_intel_crtc_state(crtc->base.state);
>  	struct intel_plane_state *plane_state =
> @@ -3227,7 +3227,27 @@ static void
> intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	if (plane->id == PLANE_PRIMARY)
> -		intel_pre_disable_primary_noatomic(&crtc->base);
> +		hsw_disable_ips(crtc_state);
> +
> +	/*
> +	 * Vblank time updates from the shadow to live plane control
> register
> +	 * are blocked if the memory self-refresh mode is active at
> that
> +	 * moment. So to make sure the plane gets truly disabled,
> disable
> +	 * first the self-refresh mode. The self-refresh enable bit in
> turn
> +	 * will be checked/applied by the HW only at the next frame
> start
> +	 * event which is after the vblank start event, so we need to
> have a
> +	 * wait-for-vblank between disabling the plane and the pipe.
> +	 */
> +	if (HAS_GMCH(dev_priv) &&
> +	    intel_set_memory_cxsr(dev_priv, false))
> +		intel_wait_for_vblank(dev_priv, crtc->pipe);
> +
> +	/*
> +	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> +	 * So disable underrun reporting before all the planes get
> disabled.
> +	 */
> +	if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc-
> >pipe, false);
>  
>  	intel_disable_plane(plane, crtc_state);
>  }
> @@ -5908,39 +5928,6 @@ static void
> intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
>  	 */
>  }
>  
> -
> -/* FIXME get rid of this and use pre_plane_update */
> -static void
> -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> -
> -	/*
> -	 * Gen2 reports pipe underruns whenever all planes are
> disabled.
> -	 * So disable underrun reporting before all the planes get
> disabled.
> -	 */
> -	if (IS_GEN(dev_priv, 2))
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
> -
> -	hsw_disable_ips(to_intel_crtc_state(crtc->state));
> -
> -	/*
> -	 * Vblank time updates from the shadow to live plane control
> register
> -	 * are blocked if the memory self-refresh mode is active at
> that
> -	 * moment. So to make sure the plane gets truly disabled,
> disable
> -	 * first the self-refresh mode. The self-refresh enable bit in
> turn
> -	 * will be checked/applied by the HW only at the next frame
> start
> -	 * event which is after the vblank start event, so we need to
> have a
> -	 * wait-for-vblank between disabling the plane and the pipe.
> -	 */
> -	if (HAS_GMCH(dev_priv) &&
> -	    intel_set_memory_cxsr(dev_priv, false))
> -		intel_wait_for_vblank(dev_priv, pipe);
> -}
> -
>  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
> *old_crtc_state,
>  				       const struct intel_crtc_state
> *new_crtc_state)
>  {
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/7] drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Assuming intel_crtc_arm_fifo_underrun() only gets called when
there's no pending plane updates we can utilize it on gen2 by
checking the active_planes bitmask so that we only re-enable
underrun reporting if some planes are active.
i915_fifo_underrun_reset_write() seems to have the necessary
hw_done/flip_done waits in place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4377ee2eee56..ec363972e0ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14221,7 +14221,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (!IS_GEN(dev_priv, 2))
+	if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
 
 	if (crtc_state->has_pch_encoder) {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 7/7] drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Assuming intel_crtc_arm_fifo_underrun() only gets called when
there's no pending plane updates we can utilize it on gen2 by
checking the active_planes bitmask so that we only re-enable
underrun reporting if some planes are active.
i915_fifo_underrun_reset_write() seems to have the necessary
hw_done/flip_done waits in place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4377ee2eee56..ec363972e0ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14221,7 +14221,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (!IS_GEN(dev_priv, 2))
+	if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
 
 	if (crtc_state->has_pch_encoder) {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/7] drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Assuming intel_crtc_arm_fifo_underrun() only gets called when
> there's no pending plane updates we can utilize it on gen2 by
> checking the active_planes bitmask so that we only re-enable
> underrun reporting if some planes are active.
> i915_fifo_underrun_reset_write() seems to have the necessary
> hw_done/flip_done waits in place.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4377ee2eee56..ec363972e0ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14221,7 +14221,7 @@ void intel_crtc_arm_fifo_underrun(struct
> intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (!IS_GEN(dev_priv, 2))
> +	if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc-
> >pipe, true);
>  
>  	if (crtc_state->has_pch_encoder) {
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2

[Souza, Jose]

On Wed, 2019-11-27 at 21:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Assuming intel_crtc_arm_fifo_underrun() only gets called when
> there's no pending plane updates we can utilize it on gen2 by
> checking the active_planes bitmask so that we only re-enable
> underrun reporting if some planes are active.
> i915_fifo_underrun_reset_write() seems to have the necessary
> hw_done/flip_done waits in place.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4377ee2eee56..ec363972e0ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14221,7 +14221,7 @@ void intel_crtc_arm_fifo_underrun(struct
> intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (!IS_GEN(dev_priv, 2))
> +	if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc-
> >pipe, true);
>  
>  	if (crtc_state->has_pch_encoder) {
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Cleanups around pre/post plane update

[Patchwork]

== Series Details ==

Series: drm/i915: Cleanups around pre/post plane update
URL   : https://patchwork.freedesktop.org/series/70125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7434 -> Patchwork_15473
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html

Known issues
------------

  Here are the changes found in Patchwork_15473 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][1] -> [FAIL][2] ([fdo#107707])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#109483])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][5] -> [FAIL][6] ([fdo#111045] / [fdo#111096])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][7] ([fdo#112261]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-icl-u3:          [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#112261]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][13] ([fdo#112147]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gt_heartbeat:
    - {fi-kbl-7560u}:     [DMESG-FAIL][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([fdo#103558] / [fdo#105602] / [fdo#107139]) -> [DMESG-WARN][18] ([fdo#103558] / [fdo#105602] / [fdo#105763] / [fdo#107139])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-kbl-x1275:       [DMESG-WARN][19] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][20] ([fdo#103558] / [fdo#105602]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-kbl-x1275:       [DMESG-WARN][21] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][22] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +5 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7434 -> Patchwork_15473

  CI-20190529: 20190529
  CI_DRM_7434: 1bbc4d30ca9fd950cbcb73f324e00d0bc357758e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5312: 851c75531043cd906e028632b64b02b9312e9945 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15473: 825c322c99519d96575675adb04bb201293bfd44 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

825c322c9951 drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2
b76390960015 drm/i915: Nuke intel_pre_disable_primary_noatomic()
fd47e7ace480 drm/i915: Clean up the gen2 "no planes -> underrun" workaround
f3c0b6f755e2 drm/i915: Clean up intel_{pre, post}_plane_update()
4c31590c8788 drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()
78efcb99f20c drm/i915: Pass dev_priv to ilk_disable_lp_wm()
ee266b9079cf drm/i915: Clean up arguments to nv12/scaler w/a funcs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Cleanups around pre/post plane update

[Patchwork]

== Series Details ==

Series: drm/i915: Cleanups around pre/post plane update
URL   : https://patchwork.freedesktop.org/series/70125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7434 -> Patchwork_15473
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html

Known issues
------------

  Here are the changes found in Patchwork_15473 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][1] -> [FAIL][2] ([fdo#107707])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#109483])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][5] -> [FAIL][6] ([fdo#111045] / [fdo#111096])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][7] ([fdo#112261]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-icl-u3:          [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#112261]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][13] ([fdo#112147]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gt_heartbeat:
    - {fi-kbl-7560u}:     [DMESG-FAIL][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-7560u/igt@i915_selftest@live_gt_heartbeat.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([fdo#103558] / [fdo#105602] / [fdo#107139]) -> [DMESG-WARN][18] ([fdo#103558] / [fdo#105602] / [fdo#105763] / [fdo#107139])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-kbl-x1275:       [DMESG-WARN][19] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][20] ([fdo#103558] / [fdo#105602]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-kbl-x1275:       [DMESG-WARN][21] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][22] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +5 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7434 -> Patchwork_15473

  CI-20190529: 20190529
  CI_DRM_7434: 1bbc4d30ca9fd950cbcb73f324e00d0bc357758e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5312: 851c75531043cd906e028632b64b02b9312e9945 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15473: 825c322c99519d96575675adb04bb201293bfd44 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

825c322c9951 drm/i915: Make intel_crtc_arm_fifo_underrun() functional on gen2
b76390960015 drm/i915: Nuke intel_pre_disable_primary_noatomic()
fd47e7ace480 drm/i915: Clean up the gen2 "no planes -> underrun" workaround
f3c0b6f755e2 drm/i915: Clean up intel_{pre, post}_plane_update()
4c31590c8788 drm/i915: s/pipe_config/new_crtc_state/ intel_{pre, post}_plane_update()
78efcb99f20c drm/i915: Pass dev_priv to ilk_disable_lp_wm()
ee266b9079cf drm/i915: Clean up arguments to nv12/scaler w/a funcs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Cleanups around pre/post plane update

[Patchwork]

== Series Details ==

Series: drm/i915: Cleanups around pre/post plane update
URL   : https://patchwork.freedesktop.org/series/70125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7434_full -> Patchwork_15473_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15473_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15473_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15473_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_balancer@bonded-chain}:
    - shard-kbl:          NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl3/igt@gem_exec_balancer@bonded-chain.html
    - shard-tglb:         NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb5/igt@gem_exec_balancer@bonded-chain.html

  
Known issues
------------

  Here are the changes found in Patchwork_15473_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#112080]) +10 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb6/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@gem_ctx_isolation@vcs1-s3.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb6/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_shared@exec-shared-gtt-bsd2:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#109276]) +7 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@gem_ctx_shared@exec-shared-gtt-bsd2.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb5/igt@gem_ctx_shared@exec-shared-gtt-bsd2.html

  * igt@gem_ctx_switch@queue-light:
    - shard-tglb:         [PASS][12] -> [INCOMPLETE][13] ([fdo#111672])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@gem_ctx_switch@queue-light.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_ctx_switch@queue-light.html

  * igt@gem_eio@in-flight-1us:
    - shard-snb:          [PASS][14] -> [FAIL][15] ([fdo#111946]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb5/igt@gem_eio@in-flight-1us.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb2/igt@gem_eio@in-flight-1us.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [PASS][16] -> [INCOMPLETE][17] ([fdo#111832] / [fdo#111850] / [fdo#112081])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb6/igt@gem_eio@in-flight-suspend.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_whisper@normal:
    - shard-tglb:         [PASS][18] -> [INCOMPLETE][19] ([fdo#111747])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb7/igt@gem_exec_whisper@normal.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb6/igt@gem_exec_whisper@normal.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-apl:          [PASS][20] -> [INCOMPLETE][21] ([fdo#103927])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-apl:          [PASS][22] -> [FAIL][23] ([fdo#102250])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl1/igt@i915_pm_rps@min-max-config-loaded.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl3/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-hsw:          [PASS][24] -> [FAIL][25] ([fdo#102887])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw5/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][26] -> [FAIL][27] ([fdo#103167])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [PASS][28] -> [FAIL][29] ([fdo#103167])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([fdo#111884])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-skl:          [PASS][32] -> [INCOMPLETE][33] ([fdo#104108])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][34] -> [DMESG-WARN][35] ([fdo#108566]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][36] -> [FAIL][37] ([fdo#108145] / [fdo#110403])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-skl:          [PASS][38] -> [DMESG-WARN][39] ([fdo#106885])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][40] -> [SKIP][41] ([fdo#109441]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][42] -> [INCOMPLETE][43] ([fdo#108972])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl6/igt@kms_psr@suspend.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl7/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [PASS][44] -> [FAIL][45] ([fdo#99912])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw1/igt@kms_setmode@basic.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw5/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@smoketest:
    - shard-glk:          [TIMEOUT][46] ([fdo#112404]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk8/igt@gem_ctx_persistence@smoketest.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk2/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_ctx_shared@q-smoketest-bsd:
    - shard-tglb:         [INCOMPLETE][48] ([fdo# 111852 ]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb9/igt@gem_ctx_shared@q-smoketest-bsd.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@gem_ctx_shared@q-smoketest-bsd.html

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [INCOMPLETE][50] ([fdo#104108]) -> [PASS][51] +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl8/igt@gem_eio@in-flight-suspend.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-hsw:          [INCOMPLETE][52] ([fdo#103540]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw4/igt@gem_eio@unwedge-stress.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_parallel@fds:
    - shard-tglb:         [INCOMPLETE][54] ([fdo#111867]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb6/igt@gem_exec_parallel@fds.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_exec_parallel@fds.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [SKIP][56] ([fdo#112146]) -> [PASS][57] +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_softpin@noreloc-s3:
    - shard-tglb:         [INCOMPLETE][58] ([fdo#111832]) -> [PASS][59] +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb3/igt@gem_softpin@noreloc-s3.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [DMESG-WARN][60] ([fdo#111870]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw7/igt@gem_userptr_blits@sync-unmap-after-close.html
    - shard-kbl:          [INCOMPLETE][62] ([fdo#103665]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl1/igt@gem_userptr_blits@sync-unmap-after-close.html
    - shard-snb:          [DMESG-WARN][64] ([fdo#111870]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-270:
    - shard-glk:          [INCOMPLETE][66] ([fdo#103359] / [k.org#198133]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk7/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html

  * igt@kms_color@pipe-c-ctm-negative:
    - shard-skl:          [FAIL][68] ([fdo#107361]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl6/igt@kms_color@pipe-c-ctm-negative.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl3/igt@kms_color@pipe-c-ctm-negative.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][70] ([fdo#107409]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk9/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
    - shard-tglb:         [INCOMPLETE][72] ([fdo#112393]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][74] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][76] ([fdo#105363]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [FAIL][78] ([fdo#100368]) -> [PASS][79] +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack:
    - shard-tglb:         [FAIL][80] ([fdo#103167]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-skl:          [INCOMPLETE][82] ([fdo#106978]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-kbl:          [INCOMPLETE][84] ([fdo#103665] / [fdo#111747]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-apl:          [DMESG-WARN][86] ([fdo#108566]) -> [PASS][87] +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][88] ([fdo#108145]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][90] ([fdo#108566]) -> [PASS][91] +10 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
    - shard-tglb:         [INCOMPLETE][92] ([fdo#111832] / [fdo#111850]) -> [PASS][93] +2 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][94] ([fdo#105411]) -> [FAIL][95] ([fdo#111757])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb1/igt@gem_eio@kms.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb6/igt@gem_eio@kms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852 
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107361]: https://bugs.freedesktop.org/show_bug.cgi?id=107361
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108972]: https://bugs.freedesktop.org/show_bug.cgi?id=108972
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#111672]: https://bugs.freedesktop.org/show_bug.cgi?id=111672
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111757]: https://bugs.freedesktop.org/show_bug.cgi?id=111757
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111946]: https://bugs.freedesktop.org/show_bug.cgi?id=111946
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112081]: https://bugs.freedesktop.org/show_bug.cgi?id=112081
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393
  [fdo#112404]: https://bugs.freedesktop.org/show_bug.cgi?id=112404
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7434 -> Patchwork_15473

  CI-20190529: 20190529
  CI_DRM_7434: 1bbc4d30ca9fd950cbcb73f324e00d0bc357758e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5312: 851c75531043cd906e028632b64b02b9312e9945 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15473: 825c322c99519d96575675adb04bb201293bfd44 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Cleanups around pre/post plane update

[Patchwork]

== Series Details ==

Series: drm/i915: Cleanups around pre/post plane update
URL   : https://patchwork.freedesktop.org/series/70125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7434_full -> Patchwork_15473_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15473_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15473_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15473_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_balancer@bonded-chain}:
    - shard-kbl:          NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl3/igt@gem_exec_balancer@bonded-chain.html
    - shard-tglb:         NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb5/igt@gem_exec_balancer@bonded-chain.html

  
Known issues
------------

  Here are the changes found in Patchwork_15473_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([fdo#112080]) +10 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb6/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@gem_ctx_isolation@vcs1-s3.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb6/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_shared@exec-shared-gtt-bsd2:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#109276]) +7 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@gem_ctx_shared@exec-shared-gtt-bsd2.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb5/igt@gem_ctx_shared@exec-shared-gtt-bsd2.html

  * igt@gem_ctx_switch@queue-light:
    - shard-tglb:         [PASS][12] -> [INCOMPLETE][13] ([fdo#111672])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@gem_ctx_switch@queue-light.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_ctx_switch@queue-light.html

  * igt@gem_eio@in-flight-1us:
    - shard-snb:          [PASS][14] -> [FAIL][15] ([fdo#111946]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb5/igt@gem_eio@in-flight-1us.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb2/igt@gem_eio@in-flight-1us.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [PASS][16] -> [INCOMPLETE][17] ([fdo#111832] / [fdo#111850] / [fdo#112081])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb6/igt@gem_eio@in-flight-suspend.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_whisper@normal:
    - shard-tglb:         [PASS][18] -> [INCOMPLETE][19] ([fdo#111747])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb7/igt@gem_exec_whisper@normal.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb6/igt@gem_exec_whisper@normal.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-apl:          [PASS][20] -> [INCOMPLETE][21] ([fdo#103927])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl4/igt@gem_userptr_blits@sync-unmap-after-close.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-apl:          [PASS][22] -> [FAIL][23] ([fdo#102250])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl1/igt@i915_pm_rps@min-max-config-loaded.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl3/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-hsw:          [PASS][24] -> [FAIL][25] ([fdo#102887])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw5/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][26] -> [FAIL][27] ([fdo#103167])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [PASS][28] -> [FAIL][29] ([fdo#103167])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([fdo#111884])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-skl:          [PASS][32] -> [INCOMPLETE][33] ([fdo#104108])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][34] -> [DMESG-WARN][35] ([fdo#108566]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][36] -> [FAIL][37] ([fdo#108145] / [fdo#110403])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-skl:          [PASS][38] -> [DMESG-WARN][39] ([fdo#106885])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][40] -> [SKIP][41] ([fdo#109441]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][42] -> [INCOMPLETE][43] ([fdo#108972])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl6/igt@kms_psr@suspend.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl7/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [PASS][44] -> [FAIL][45] ([fdo#99912])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw1/igt@kms_setmode@basic.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw5/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@smoketest:
    - shard-glk:          [TIMEOUT][46] ([fdo#112404]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk8/igt@gem_ctx_persistence@smoketest.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk2/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_ctx_shared@q-smoketest-bsd:
    - shard-tglb:         [INCOMPLETE][48] ([fdo# 111852 ]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb9/igt@gem_ctx_shared@q-smoketest-bsd.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@gem_ctx_shared@q-smoketest-bsd.html

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [INCOMPLETE][50] ([fdo#104108]) -> [PASS][51] +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl8/igt@gem_eio@in-flight-suspend.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-hsw:          [INCOMPLETE][52] ([fdo#103540]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw4/igt@gem_eio@unwedge-stress.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_parallel@fds:
    - shard-tglb:         [INCOMPLETE][54] ([fdo#111867]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb6/igt@gem_exec_parallel@fds.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@gem_exec_parallel@fds.html

  * igt@gem_exec_schedule@preempt-queue-bsd:
    - shard-iclb:         [SKIP][56] ([fdo#112146]) -> [PASS][57] +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd.html

  * igt@gem_softpin@noreloc-s3:
    - shard-tglb:         [INCOMPLETE][58] ([fdo#111832]) -> [PASS][59] +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb3/igt@gem_softpin@noreloc-s3.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [DMESG-WARN][60] ([fdo#111870]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-hsw7/igt@gem_userptr_blits@sync-unmap-after-close.html
    - shard-kbl:          [INCOMPLETE][62] ([fdo#103665]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl1/igt@gem_userptr_blits@sync-unmap-after-close.html
    - shard-snb:          [DMESG-WARN][64] ([fdo#111870]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-270:
    - shard-glk:          [INCOMPLETE][66] ([fdo#103359] / [k.org#198133]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk7/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk4/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html

  * igt@kms_color@pipe-c-ctm-negative:
    - shard-skl:          [FAIL][68] ([fdo#107361]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl6/igt@kms_color@pipe-c-ctm-negative.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl3/igt@kms_color@pipe-c-ctm-negative.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][70] ([fdo#107409]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-glk9/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-glk3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
    - shard-tglb:         [INCOMPLETE][72] ([fdo#112393]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][74] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][76] ([fdo#105363]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [FAIL][78] ([fdo#100368]) -> [PASS][79] +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack:
    - shard-tglb:         [FAIL][80] ([fdo#103167]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-skl:          [INCOMPLETE][82] ([fdo#106978]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-kbl:          [INCOMPLETE][84] ([fdo#103665] / [fdo#111747]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-apl:          [DMESG-WARN][86] ([fdo#108566]) -> [PASS][87] +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][88] ([fdo#108145]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][90] ([fdo#108566]) -> [PASS][91] +10 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
    - shard-tglb:         [INCOMPLETE][92] ([fdo#111832] / [fdo#111850]) -> [PASS][93] +2 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-tglb5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-tglb2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][94] ([fdo#105411]) -> [FAIL][95] ([fdo#111757])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7434/shard-snb1/igt@gem_eio@kms.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/shard-snb6/igt@gem_eio@kms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852 
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107361]: https://bugs.freedesktop.org/show_bug.cgi?id=107361
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108972]: https://bugs.freedesktop.org/show_bug.cgi?id=108972
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#111672]: https://bugs.freedesktop.org/show_bug.cgi?id=111672
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111757]: https://bugs.freedesktop.org/show_bug.cgi?id=111757
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111946]: https://bugs.freedesktop.org/show_bug.cgi?id=111946
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112081]: https://bugs.freedesktop.org/show_bug.cgi?id=112081
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393
  [fdo#112404]: https://bugs.freedesktop.org/show_bug.cgi?id=112404
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7434 -> Patchwork_15473

  CI-20190529: 20190529
  CI_DRM_7434: 1bbc4d30ca9fd950cbcb73f324e00d0bc357758e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5312: 851c75531043cd906e028632b64b02b9312e9945 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15473: 825c322c99519d96575675adb04bb201293bfd44 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15473/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx