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* [Intel-gfx] [PATCH] drm/i915/dsb: Fix in mmio offset calculation of DSB instance
@ 2019-12-05 12:35 Animesh Manna
  2019-12-05 12:46 ` Anshuamn Gupta
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Animesh Manna @ 2019-12-05 12:35 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

As the current usage is restricted to first DSB instance per pipe, so
existing code could not catch the issue to calculate the mmio offset
of different DSB instance per pipe. Corrected the offset calculation.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a6376a97d48..0b242513e3eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12076,7 +12076,7 @@ enum skl_power_gate {
 /* This register controls the Display State Buffer (DSB) engines. */
 #define _DSBSL_INSTANCE_BASE		0x70B00
 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
-					 (pipe) * 0x1000 + (id) * 100)
+					 (pipe) * 0x1000 + (id) * 0x100)
 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
-- 
2.22.0

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^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-12-11 10:27 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-12-05 12:35 [Intel-gfx] [PATCH] drm/i915/dsb: Fix in mmio offset calculation of DSB instance Animesh Manna
2019-12-05 12:46 ` Anshuamn Gupta
2019-12-11 10:27   ` Jani Nikula
2019-12-05 14:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2019-12-05 19:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2019-12-09  7:01 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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