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From: Shawn Guo <shawnguo@kernel.org>
To: Anson Huang <Anson.Huang@nxp.com>
Cc: gregkh@linuxfoundation.org, s.hauer@pengutronix.de,
	linux@armlinux.org.uk, linux-kernel@vger.kernel.org,
	Linux-imx@nxp.com, kernel@pengutronix.de, tglx@linutronix.de,
	festevam@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2] ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
Date: Wed, 11 Dec 2019 11:40:25 +0800	[thread overview]
Message-ID: <20191211034024.GI15858@dragon> (raw)
In-Reply-To: <1576032816-23373-1-git-send-email-Anson.Huang@nxp.com>

On Wed, Dec 11, 2019 at 10:53:36AM +0800, Anson Huang wrote:
> ARM_ERRATA_814220 has below description:
> 
> The v7 ARM states that all cache and branch predictor maintenance
> operations that do not specify an address execute, relative to
> each other, in program order.
> However, because of this erratum, an L2 set/way cache maintenance
> operation can overtake an L1 set/way cache maintenance operation.
> This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
> r0p4, r0p5.
> 
> i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable
> ARM_ERRATA_814220 for proper workaround.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Applied, thanks.

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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Anson Huang <Anson.Huang@nxp.com>
Cc: linux@armlinux.org.uk, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, tglx@linutronix.de,
	gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Linux-imx@nxp.com
Subject: Re: [PATCH V2] ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
Date: Wed, 11 Dec 2019 11:40:25 +0800	[thread overview]
Message-ID: <20191211034024.GI15858@dragon> (raw)
In-Reply-To: <1576032816-23373-1-git-send-email-Anson.Huang@nxp.com>

On Wed, Dec 11, 2019 at 10:53:36AM +0800, Anson Huang wrote:
> ARM_ERRATA_814220 has below description:
> 
> The v7 ARM states that all cache and branch predictor maintenance
> operations that do not specify an address execute, relative to
> each other, in program order.
> However, because of this erratum, an L2 set/way cache maintenance
> operation can overtake an L1 set/way cache maintenance operation.
> This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
> r0p4, r0p5.
> 
> i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable
> ARM_ERRATA_814220 for proper workaround.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Applied, thanks.

  reply	other threads:[~2019-12-11  3:40 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-11  2:53 [PATCH V2] ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D Anson Huang
2019-12-11  2:53 ` Anson Huang
2019-12-11  3:40 ` Shawn Guo [this message]
2019-12-11  3:40   ` Shawn Guo

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