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From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
To: Michael Ellerman <mpe@ellerman.id.au>
Cc: andmike@linux.ibm.com, linuxram@us.ibm.com,
	kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org,
	Sukadev Bhattiprolu <sukadev@linux.ibm.com>,
	bauerman@linux.ibm.com
Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs
Date: Wed, 18 Dec 2019 23:57:53 +0000	[thread overview]
Message-ID: <20191218235753.GA12285@us.ibm.com> (raw)
In-Reply-To: <875zidoqok.fsf@mpe.ellerman.id.au>

Michael Ellerman [mpe@ellerman.id.au] wrote:
> 
> eg. here.
> 
> This is the fast path of context switch.
> 
> That expands to:
> 
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval));
> 

Yes, should have optimized this at least :-)
> 
> If the Ultravisor is going to disable EBB and BHRB then we need new
> CPU_FTR bits for those, and the code that accesses those registers
> needs to be put behind cpu_has_feature(EBB) etc.

Will try the cpu_has_feature(). Would it be ok to use a single feature
bit, like UV or make it per-register group as that could need more
feature bits?

Thanks,

Sukadev

WARNING: multiple messages have this Message-ID (diff)
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
To: Michael Ellerman <mpe@ellerman.id.au>
Cc: andmike@linux.ibm.com, linuxram@us.ibm.com,
	kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org,
	Sukadev Bhattiprolu <sukadev@linux.ibm.com>,
	bauerman@linux.ibm.com
Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs
Date: Wed, 18 Dec 2019 15:57:53 -0800	[thread overview]
Message-ID: <20191218235753.GA12285@us.ibm.com> (raw)
In-Reply-To: <875zidoqok.fsf@mpe.ellerman.id.au>

Michael Ellerman [mpe@ellerman.id.au] wrote:
> 
> eg. here.
> 
> This is the fast path of context switch.
> 
> That expands to:
> 
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval));
> 

Yes, should have optimized this at least :-)
> 
> If the Ultravisor is going to disable EBB and BHRB then we need new
> CPU_FTR bits for those, and the code that accesses those registers
> needs to be put behind cpu_has_feature(EBB) etc.

Will try the cpu_has_feature(). Would it be ok to use a single feature
bit, like UV or make it per-register group as that could need more
feature bits?

Thanks,

Sukadev

  reply	other threads:[~2019-12-18 23:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-18  4:30 [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Sukadev Bhattiprolu
2019-12-18  4:30 ` Sukadev Bhattiprolu
2019-12-18  4:30 ` [PATCH 2/2] powerpc/pseries/svm: Disable PMUs in SVMs Sukadev Bhattiprolu
2019-12-18  4:30   ` Sukadev Bhattiprolu
2019-12-18 10:48 ` [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs Michael Ellerman
2019-12-18 10:48   ` Michael Ellerman
2019-12-18 23:57   ` Sukadev Bhattiprolu [this message]
2019-12-18 23:57     ` Sukadev Bhattiprolu
2019-12-19 10:59     ` Michael Ellerman
2019-12-19 10:59       ` Michael Ellerman

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