From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
manasi.d.navare@intel.com, uma.shankar@intel.com,
anshuman.gupta@intel.com
Subject: Re: [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
Date: Thu, 19 Dec 2019 14:33:10 +0200 [thread overview]
Message-ID: <20191219123310.GG1208@intel.com> (raw)
In-Reply-To: <20191218151350.19579-4-animesh.manna@intel.com>
On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
>
> No functional change.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
> 3 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
> }
> }
>
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status)
I'd prefer to keep the arrayish notation so we have some idea how big
this is supposed to be. I guess that woukld mean including some
drm dp header in intel_dp.h?
> +{
> + u8 v = 0;
> + u8 p = 0;
> + int lane;
> + u8 voltage_max;
> + u8 preemph_max;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++) {
> + u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> + if (this_v > v)
> + v = this_v;
> + if (this_p > p)
> + p = this_p;
> + }
> +
> + voltage_max = intel_dp_voltage_max(intel_dp);
> + if (v >= voltage_max)
> + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> + preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> + if (p >= preemph_max)
> + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> + for (lane = 0; lane < 4; lane++)
> + intel_dp->train_set[lane] = v | p;
> +}
> +
> void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat);
> void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status);
> +void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> link_status[3], link_status[4], link_status[5]);
> }
>
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> - const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - u8 v = 0;
> - u8 p = 0;
> - int lane;
> - u8 voltage_max;
> - u8 preemph_max;
> -
> - for (lane = 0; lane < intel_dp->lane_count; lane++) {
> - u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> - u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> - if (this_v > v)
> - v = this_v;
> - if (this_p > p)
> - p = this_p;
> - }
> -
> - voltage_max = intel_dp_voltage_max(intel_dp);
> - if (v >= voltage_max)
> - v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> - preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> - if (p >= preemph_max)
> - p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> - for (lane = 0; lane < 4; lane++)
> - intel_dp->train_set[lane] = v | p;
> -}
> -
> static bool
> intel_dp_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> --
> 2.24.0
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
Date: Thu, 19 Dec 2019 14:33:10 +0200 [thread overview]
Message-ID: <20191219123310.GG1208@intel.com> (raw)
In-Reply-To: <20191218151350.19579-4-animesh.manna@intel.com>
On Wed, Dec 18, 2019 at 08:43:44PM +0530, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
>
> No functional change.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> .../drm/i915/display/intel_dp_link_training.c | 32 -------------------
> 3 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2f31d226c6eb..ca82835b6dcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
> }
> }
>
> +void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status)
I'd prefer to keep the arrayish notation so we have some idea how big
this is supposed to be. I guess that woukld mean including some
drm dp header in intel_dp.h?
> +{
> + u8 v = 0;
> + u8 p = 0;
> + int lane;
> + u8 voltage_max;
> + u8 preemph_max;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++) {
> + u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> +
> + if (this_v > v)
> + v = this_v;
> + if (this_p > p)
> + p = this_p;
> + }
> +
> + voltage_max = intel_dp_voltage_max(intel_dp);
> + if (v >= voltage_max)
> + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> + preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> + if (p >= preemph_max)
> + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> + for (lane = 0; lane < 4; lane++)
> + intel_dp->train_set[lane] = v | p;
> +}
> +
> void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..0d0cb692f701 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -91,6 +91,9 @@ void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat);
> void
> +intel_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 *link_status);
> +void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..1e38584e7d56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
> link_status[3], link_status[4], link_status[5]);
> }
>
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> - const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - u8 v = 0;
> - u8 p = 0;
> - int lane;
> - u8 voltage_max;
> - u8 preemph_max;
> -
> - for (lane = 0; lane < intel_dp->lane_count; lane++) {
> - u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
> - u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
> -
> - if (this_v > v)
> - v = this_v;
> - if (this_p > p)
> - p = this_p;
> - }
> -
> - voltage_max = intel_dp_voltage_max(intel_dp);
> - if (v >= voltage_max)
> - v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> - preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> - if (p >= preemph_max)
> - p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> - for (lane = 0; lane < 4; lane++)
> - intel_dp->train_set[lane] = v | p;
> -}
> -
> static bool
> intel_dp_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> --
> 2.24.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-12-19 12:33 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 15:13 [PATCH v2 0/9] DP Phy compliance auto test Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 1/9] drm/dp: get/set phy compliance pattern Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 2/9] drm/amd/display: Fix compilation issue Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:42 ` Harry Wentland
2019-12-18 15:42 ` [Intel-gfx] " Harry Wentland
2019-12-18 16:13 ` Manna, Animesh
2019-12-18 16:13 ` [Intel-gfx] " Manna, Animesh
2019-12-18 16:22 ` Harry Wentland
2019-12-18 16:22 ` [Intel-gfx] " Harry Wentland
2019-12-18 23:53 ` Manasi Navare
2019-12-18 23:53 ` [Intel-gfx] " Manasi Navare
2019-12-19 13:36 ` Manna, Animesh
2019-12-19 13:36 ` [Intel-gfx] " Manna, Animesh
2019-12-23 17:03 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Animesh Manna
2019-12-23 17:03 ` [Intel-gfx] " Animesh Manna
2019-12-23 17:03 ` [PATCH v3 2/9] drm/dp: get/set phy compliance pattern Animesh Manna
2019-12-23 17:03 ` [Intel-gfx] " Animesh Manna
2019-12-23 19:53 ` Harry Wentland
2019-12-23 19:53 ` [Intel-gfx] " Harry Wentland
2019-12-30 16:05 ` Manna, Animesh
2019-12-30 16:05 ` [Intel-gfx] " Manna, Animesh
2019-12-30 16:11 ` Harry Wentland
2019-12-30 16:11 ` [Intel-gfx] " Harry Wentland
2019-12-30 16:30 ` Manna, Animesh
2019-12-30 16:30 ` [Intel-gfx] " Manna, Animesh
2019-12-23 19:53 ` [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec Harry Wentland
2019-12-23 19:53 ` [Intel-gfx] " Harry Wentland
2019-12-18 15:13 ` [PATCH v2 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-19 10:51 ` Jani Nikula
2019-12-19 10:51 ` [Intel-gfx] " Jani Nikula
2019-12-19 13:27 ` Manna, Animesh
2019-12-19 13:27 ` [Intel-gfx] " Manna, Animesh
2019-12-19 12:33 ` Ville Syrjälä [this message]
2019-12-19 12:33 ` Ville Syrjälä
2019-12-19 13:31 ` Manna, Animesh
2019-12-19 13:31 ` [Intel-gfx] " Manna, Animesh
2019-12-23 16:45 ` [PATCH v3 " Animesh Manna
2019-12-23 16:45 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 4/9] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 5/9] drm/i915/dsb: Send uevent to testapp Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 7/9] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 8/9] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 15:13 ` [PATCH v2 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-12-18 15:13 ` [Intel-gfx] " Animesh Manna
2019-12-18 18:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test Patchwork
2019-12-18 18:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2019-12-18 19:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2019-12-20 4:31 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2019-12-23 19:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DP Phy compliance auto test (rev4) Patchwork
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