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From: Miquel Raynal <miquel.raynal-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: "Heiko Stübner" <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Maxime Chevallier
	<maxime.chevallier-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
	Paul Kocialkowski
	<paul.kocialkowski-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Thomas Petazzoni
	<thomas.petazzoni-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
Subject: Re: [PATCH] arm64: dts: rockchip: Describe PX30 caches
Date: Mon, 23 Dec 2019 10:03:20 +0100	[thread overview]
Message-ID: <20191223100320.3b852485@xps13> (raw)
In-Reply-To: <1982322.8UTTk47u2F@diego>

Hi Heiko,

Heiko Stübner <heiko@sntech.de> wrote on Fri, 20 Dec 2019 01:55:58
+0100:

> Am Mittwoch, 4. Dezember 2019, 11:39:40 CET schrieb Miquel Raynal:
> > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > Cortex-A35manual).
> > 
> > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > is 8-way set associative (ARM Cortex-A35 manual).
> > 
> > Describe all of them in the PX30 DTSI.
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index 1fd12bd09e83..0e10a224a84b 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -48,6 +48,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu1: cpu@1 {
> > @@ -60,6 +67,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu2: cpu@2 {
> > @@ -72,6 +86,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu3: cpu@3 {
> > @@ -84,6 +105,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		idle-states {
> > @@ -107,6 +135,13 @@
> >  				min-residency-us = <2000>;
> >  			};
> >  		};
> > +
> > +		l2: l2-cache {
> > +			compatible = "cache";
> > +			cache-size = <0x40000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <512>;
> > +		};
> >  	};  
> 
> Looks like Rob did answer my unspoken question, citing his reply to
> 	"arm64: dts: amazon: add Amazon's Annapurna Labs Alpine v3 support" [0]
> 
> "We only define cache attributes if not discoverable or the cache ID 
> registers are wrong and you need to override what's discoverable."
> 
> So unless the cache information read during boot is wrong, it looks
> like we don't need this.

Well, I actually met the:

         "Unable to detect cache hierarchy for CPU <x>"

warning in the dmesg. Do you know anything about cache ID registers?

There is some kind of "i-cache" infos [TRM page 391] but it doesn't
seem enough to describe the cache hierarchy.

> 
> Heiko
> 
> 
> [0] https://patchwork.kernel.org/patch/11279705/

Thanks,
Miquèl

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org,
	Paul Kocialkowski <paul.kocialkowski@bootlin.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH] arm64: dts: rockchip: Describe PX30 caches
Date: Mon, 23 Dec 2019 10:03:20 +0100	[thread overview]
Message-ID: <20191223100320.3b852485@xps13> (raw)
In-Reply-To: <1982322.8UTTk47u2F@diego>

Hi Heiko,

Heiko Stübner <heiko@sntech.de> wrote on Fri, 20 Dec 2019 01:55:58
+0100:

> Am Mittwoch, 4. Dezember 2019, 11:39:40 CET schrieb Miquel Raynal:
> > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > Cortex-A35manual).
> > 
> > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > is 8-way set associative (ARM Cortex-A35 manual).
> > 
> > Describe all of them in the PX30 DTSI.
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index 1fd12bd09e83..0e10a224a84b 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -48,6 +48,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu1: cpu@1 {
> > @@ -60,6 +67,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu2: cpu@2 {
> > @@ -72,6 +86,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu3: cpu@3 {
> > @@ -84,6 +105,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		idle-states {
> > @@ -107,6 +135,13 @@
> >  				min-residency-us = <2000>;
> >  			};
> >  		};
> > +
> > +		l2: l2-cache {
> > +			compatible = "cache";
> > +			cache-size = <0x40000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <512>;
> > +		};
> >  	};  
> 
> Looks like Rob did answer my unspoken question, citing his reply to
> 	"arm64: dts: amazon: add Amazon's Annapurna Labs Alpine v3 support" [0]
> 
> "We only define cache attributes if not discoverable or the cache ID 
> registers are wrong and you need to override what's discoverable."
> 
> So unless the cache information read during boot is wrong, it looks
> like we don't need this.

Well, I actually met the:

         "Unable to detect cache hierarchy for CPU <x>"

warning in the dmesg. Do you know anything about cache ID registers?

There is some kind of "i-cache" infos [TRM page 391] but it doesn't
seem enough to describe the cache hierarchy.

> 
> Heiko
> 
> 
> [0] https://patchwork.kernel.org/patch/11279705/

Thanks,
Miquèl

  reply	other threads:[~2019-12-23  9:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-04 10:39 [PATCH] arm64: dts: rockchip: Describe PX30 caches Miquel Raynal
2019-12-04 10:39 ` Miquel Raynal
     [not found] ` <20191204103940.22050-1-miquel.raynal-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
2019-12-04 15:36   ` Peter Geis
2019-12-04 15:36     ` Peter Geis
     [not found]     ` <CAMdYzYrEmTqvJ6m54EADxLDf70duCtdz3pesV3EZmt67=cbs5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-12-04 15:44       ` Miquel Raynal
2019-12-04 15:44         ` Miquel Raynal
2019-12-04 17:14         ` Peter Geis
2019-12-04 17:14           ` Peter Geis
     [not found]           ` <CAMdYzYoUo_M+qEp3HRsEGrGJDa73JACfH38HG7aY6C8NrQi=5A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-12-04 17:17             ` Miquel Raynal
2019-12-04 17:17               ` Miquel Raynal
2019-12-20  0:55   ` Heiko Stübner
2019-12-20  0:55     ` Heiko Stübner
2019-12-23  9:03     ` Miquel Raynal [this message]
2019-12-23  9:03       ` Miquel Raynal

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