* [PATCHv3 0/3] Odroid n2 using eMMC would fail to boot up
@ 2019-12-26 11:33 ` Anand Moon
0 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: u-boot
Here are some small changes to fix booting of Odroid N2 using eMMC.
Fixed the clk tunnig during mmc initialization.
Build and tested on top of below patches
[0] https://patchwork.ozlabs.org/patch/1213648/
[1] https://patchwork.ozlabs.org/patch/1213650/
Tested on below eMMC module on Odroid N2 and C2
new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
old back - eMMC CGND3R 58.2 GiB MMC 5.0
Prevoius changes:
Fixed the clk tuning as per mainline kernel
[3]v1 https://patchwork.ozlabs.org/cover/1201206/
[4]v2 https://patchwork.ozlabs.org/cover/1215217/
-Anand
Anand Moon (3):
mmc: meson-gx: Fix clk phase tuning for MMC
configs: meson64: enable GIC support for G12A/G12B
board: amlogic: select PWRSEQ for all amlogic platform
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
arch/arm/mach-meson/Kconfig | 1 +
drivers/mmc/meson_gx_mmc.c | 9 +++++----
include/configs/meson64.h | 2 +-
4 files changed, 13 insertions(+), 13 deletions(-)
--
2.24.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
2019-12-26 11:33 ` Anand Moon
@ 2019-12-26 11:33 ` Anand Moon
-1 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: Neil Armstrong, Peng Fan, Jerome Brunet, u-boot-amlogic, u-boot
As per mainline line kernel fix the clk tunnig phase for
mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Changes from previous
v2: Fix the clk phase macro to support PHASE_180
drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages.
Patch v1:
https://patchwork.ozlabs.org/patch/1201208/
Before these changes.
clock is enabled (380953Hz)
clock is enabled (25000000Hz)
After these changes
clock is enabled (380953Hz)
clock is enabled (25000000Hz)
clock is enabled (52000000Hz)
Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
drivers/mmc/meson_gx_mmc.c | 9 +++++----
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..ee20c009e2 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
#define __SD_EMMC_H__
#include <mmc.h>
+#include <linux/bitops.h>
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
@@ -19,14 +20,11 @@
#define CLK_MAX_DIV 63
#define CLK_SRC_24M (0 << 6)
#define CLK_SRC_DIV2 (1 << 6)
-#define CLK_CO_PHASE_000 (0 << 8)
-#define CLK_CO_PHASE_090 (1 << 8)
-#define CLK_CO_PHASE_180 (2 << 8)
-#define CLK_CO_PHASE_270 (3 << 8)
-#define CLK_TX_PHASE_000 (0 << 10)
-#define CLK_TX_PHASE_090 (1 << 10)
-#define CLK_TX_PHASE_180 (2 << 10)
-#define CLK_TX_PHASE_270 (3 << 10)
+
+#define CLK_PHASE_180 2
+#define CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define CLK_RX_PHASE_MASK GENMASK(13, 12)
+
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..ad697d3a5e 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
-
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
+ meson_mmc_clk |= CLK_PHASE_180;
+ /* 000 phase rx clock */
+ meson_mmc_clk |= CLK_RX_PHASE_MASK;
+ /* 000 phase tx clock */
+ meson_mmc_clk |= CLK_TX_PHASE_MASK;
/* clock settings */
meson_mmc_clk |= clk_src;
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2019-12-26 11:33 ` Anand Moon
0 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: u-boot
As per mainline line kernel fix the clk tunnig phase for
mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Changes from previous
v2: Fix the clk phase macro to support PHASE_180
drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages.
Patch v1:
https://patchwork.ozlabs.org/patch/1201208/
Before these changes.
clock is enabled (380953Hz)
clock is enabled (25000000Hz)
After these changes
clock is enabled (380953Hz)
clock is enabled (25000000Hz)
clock is enabled (52000000Hz)
Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
drivers/mmc/meson_gx_mmc.c | 9 +++++----
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..ee20c009e2 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
#define __SD_EMMC_H__
#include <mmc.h>
+#include <linux/bitops.h>
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
@@ -19,14 +20,11 @@
#define CLK_MAX_DIV 63
#define CLK_SRC_24M (0 << 6)
#define CLK_SRC_DIV2 (1 << 6)
-#define CLK_CO_PHASE_000 (0 << 8)
-#define CLK_CO_PHASE_090 (1 << 8)
-#define CLK_CO_PHASE_180 (2 << 8)
-#define CLK_CO_PHASE_270 (3 << 8)
-#define CLK_TX_PHASE_000 (0 << 10)
-#define CLK_TX_PHASE_090 (1 << 10)
-#define CLK_TX_PHASE_180 (2 << 10)
-#define CLK_TX_PHASE_270 (3 << 10)
+
+#define CLK_PHASE_180 2
+#define CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define CLK_RX_PHASE_MASK GENMASK(13, 12)
+
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..ad697d3a5e 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
-
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
+ meson_mmc_clk |= CLK_PHASE_180;
+ /* 000 phase rx clock */
+ meson_mmc_clk |= CLK_RX_PHASE_MASK;
+ /* 000 phase tx clock */
+ meson_mmc_clk |= CLK_TX_PHASE_MASK;
/* clock settings */
meson_mmc_clk |= clk_src;
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
2019-12-26 11:33 ` Anand Moon
@ 2020-01-07 10:00 ` Jerome Brunet
-1 siblings, 0 replies; 18+ messages in thread
From: Jerome Brunet @ 2020-01-07 10:00 UTC (permalink / raw)
To: Anand Moon, Neil Armstrong, Peng Fan, u-boot-amlogic, u-boot
On Thu 26 Dec 2019 at 12:33, Anand Moon <linux.amoon@gmail.com> wrote:
> As per mainline line kernel fix the clk tunnig phase for
> mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Changes from previous
> v2: Fix the clk phase macro to support PHASE_180
> drop the wrong CLK_CORE_PHASE_MASK macro.
>
> v1: use the mainline kernel tuning for clk tuning.
> Fixed the commmit messages.
> Patch v1:
> https://patchwork.ozlabs.org/patch/1201208/
>
> Before these changes.
> clock is enabled (380953Hz)
> clock is enabled (25000000Hz)
> After these changes
> clock is enabled (380953Hz)
> clock is enabled (25000000Hz)
> clock is enabled (52000000Hz)
> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> ---
> arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
> drivers/mmc/meson_gx_mmc.c | 9 +++++----
> 2 files changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..ee20c009e2 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
> #define __SD_EMMC_H__
>
> #include <mmc.h>
> +#include <linux/bitops.h>
>
> #define SDIO_PORT_A 0
> #define SDIO_PORT_B 1
> @@ -19,14 +20,11 @@
> #define CLK_MAX_DIV 63
> #define CLK_SRC_24M (0 << 6)
> #define CLK_SRC_DIV2 (1 << 6)
> -#define CLK_CO_PHASE_000 (0 << 8)
> -#define CLK_CO_PHASE_090 (1 << 8)
> -#define CLK_CO_PHASE_180 (2 << 8)
> -#define CLK_CO_PHASE_270 (3 << 8)
> -#define CLK_TX_PHASE_000 (0 << 10)
> -#define CLK_TX_PHASE_090 (1 << 10)
> -#define CLK_TX_PHASE_180 (2 << 10)
> -#define CLK_TX_PHASE_270 (3 << 10)
> +
> +#define CLK_PHASE_180 2
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +
> #define CLK_ALWAYS_ON BIT(24)
>
> #define MESON_SD_EMMC_CFG 0x44
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..ad697d3a5e 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> /* 180 phase core clock */
> - meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> - /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + meson_mmc_clk |= CLK_PHASE_180;
> + /* 000 phase rx clock */
> + meson_mmc_clk |= CLK_RX_PHASE_MASK;
> + /* 000 phase tx clock */
> + meson_mmc_clk |= CLK_TX_PHASE_MASK;
The comment on your previous version seemed correct but I think what you
have implemented here is still not doing what you expect.
>
> /* clock settings */
> meson_mmc_clk |= clk_src;
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-01-07 10:00 ` Jerome Brunet
0 siblings, 0 replies; 18+ messages in thread
From: Jerome Brunet @ 2020-01-07 10:00 UTC (permalink / raw)
To: u-boot
On Thu 26 Dec 2019 at 12:33, Anand Moon <linux.amoon@gmail.com> wrote:
> As per mainline line kernel fix the clk tunnig phase for
> mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Changes from previous
> v2: Fix the clk phase macro to support PHASE_180
> drop the wrong CLK_CORE_PHASE_MASK macro.
>
> v1: use the mainline kernel tuning for clk tuning.
> Fixed the commmit messages.
> Patch v1:
> https://patchwork.ozlabs.org/patch/1201208/
>
> Before these changes.
> clock is enabled (380953Hz)
> clock is enabled (25000000Hz)
> After these changes
> clock is enabled (380953Hz)
> clock is enabled (25000000Hz)
> clock is enabled (52000000Hz)
> Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> ---
> arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
> drivers/mmc/meson_gx_mmc.c | 9 +++++----
> 2 files changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..ee20c009e2 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
> #define __SD_EMMC_H__
>
> #include <mmc.h>
> +#include <linux/bitops.h>
>
> #define SDIO_PORT_A 0
> #define SDIO_PORT_B 1
> @@ -19,14 +20,11 @@
> #define CLK_MAX_DIV 63
> #define CLK_SRC_24M (0 << 6)
> #define CLK_SRC_DIV2 (1 << 6)
> -#define CLK_CO_PHASE_000 (0 << 8)
> -#define CLK_CO_PHASE_090 (1 << 8)
> -#define CLK_CO_PHASE_180 (2 << 8)
> -#define CLK_CO_PHASE_270 (3 << 8)
> -#define CLK_TX_PHASE_000 (0 << 10)
> -#define CLK_TX_PHASE_090 (1 << 10)
> -#define CLK_TX_PHASE_180 (2 << 10)
> -#define CLK_TX_PHASE_270 (3 << 10)
> +
> +#define CLK_PHASE_180 2
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +
> #define CLK_ALWAYS_ON BIT(24)
>
> #define MESON_SD_EMMC_CFG 0x44
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..ad697d3a5e 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> /* 180 phase core clock */
> - meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> - /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + meson_mmc_clk |= CLK_PHASE_180;
> + /* 000 phase rx clock */
> + meson_mmc_clk |= CLK_RX_PHASE_MASK;
> + /* 000 phase tx clock */
> + meson_mmc_clk |= CLK_TX_PHASE_MASK;
The comment on your previous version seemed correct but I think what you
have implemented here is still not doing what you expect.
>
> /* clock settings */
> meson_mmc_clk |= clk_src;
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
2020-01-07 10:00 ` Jerome Brunet
@ 2020-01-11 12:23 ` Anand Moon
-1 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2020-01-11 12:23 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Peng Fan, u-boot-amlogic, U-Boot Mailing List
Hi Jerome,
On Tue, 7 Jan 2020 at 15:31, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Thu 26 Dec 2019 at 12:33, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > As per mainline line kernel fix the clk tunnig phase for
> > mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > Changes from previous
> > v2: Fix the clk phase macro to support PHASE_180
> > drop the wrong CLK_CORE_PHASE_MASK macro.
> >
> > v1: use the mainline kernel tuning for clk tuning.
> > Fixed the commmit messages.
> > Patch v1:
> > https://patchwork.ozlabs.org/patch/1201208/
> >
> > Before these changes.
> > clock is enabled (380953Hz)
> > clock is enabled (25000000Hz)
> > After these changes
> > clock is enabled (380953Hz)
> > clock is enabled (25000000Hz)
> > clock is enabled (52000000Hz)
> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> > ---
> > arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
> > drivers/mmc/meson_gx_mmc.c | 9 +++++----
> > 2 files changed, 11 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..ee20c009e2 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> > #define __SD_EMMC_H__
> >
> > #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> > #define SDIO_PORT_A 0
> > #define SDIO_PORT_B 1
> > @@ -19,14 +20,11 @@
> > #define CLK_MAX_DIV 63
> > #define CLK_SRC_24M (0 << 6)
> > #define CLK_SRC_DIV2 (1 << 6)
> > -#define CLK_CO_PHASE_000 (0 << 8)
> > -#define CLK_CO_PHASE_090 (1 << 8)
> > -#define CLK_CO_PHASE_180 (2 << 8)
> > -#define CLK_CO_PHASE_270 (3 << 8)
> > -#define CLK_TX_PHASE_000 (0 << 10)
> > -#define CLK_TX_PHASE_090 (1 << 10)
> > -#define CLK_TX_PHASE_180 (2 << 10)
> > -#define CLK_TX_PHASE_270 (3 << 10)
> > +
> > +#define CLK_PHASE_180 2
> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> > +
> > #define CLK_ALWAYS_ON BIT(24)
> >
> > #define MESON_SD_EMMC_CFG 0x44
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..ad697d3a5e 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > /* 180 phase core clock */
> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > - /* 180 phase tx clock */
> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> > + meson_mmc_clk |= CLK_PHASE_180;
> > + /* 000 phase rx clock */
> > + meson_mmc_clk |= CLK_RX_PHASE_MASK;
> > + /* 000 phase tx clock */
> > + meson_mmc_clk |= CLK_TX_PHASE_MASK;
>
> The comment on your previous version seemed correct but I think what you
> have implemented here is still not doing what you expect.
Thanks for your review. Ok I admit, I did not study the code correctly and
it's wrong to set this way. Plz discard this changes it's wrong.
It did not worked for some sdcards and emmc.
-Anand
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-01-11 12:23 ` Anand Moon
0 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2020-01-11 12:23 UTC (permalink / raw)
To: u-boot
Hi Jerome,
On Tue, 7 Jan 2020 at 15:31, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Thu 26 Dec 2019 at 12:33, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > As per mainline line kernel fix the clk tunnig phase for
> > mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > Changes from previous
> > v2: Fix the clk phase macro to support PHASE_180
> > drop the wrong CLK_CORE_PHASE_MASK macro.
> >
> > v1: use the mainline kernel tuning for clk tuning.
> > Fixed the commmit messages.
> > Patch v1:
> > https://patchwork.ozlabs.org/patch/1201208/
> >
> > Before these changes.
> > clock is enabled (380953Hz)
> > clock is enabled (25000000Hz)
> > After these changes
> > clock is enabled (380953Hz)
> > clock is enabled (25000000Hz)
> > clock is enabled (52000000Hz)
> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
> > ---
> > arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++--------
> > drivers/mmc/meson_gx_mmc.c | 9 +++++----
> > 2 files changed, 11 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..ee20c009e2 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> > #define __SD_EMMC_H__
> >
> > #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> > #define SDIO_PORT_A 0
> > #define SDIO_PORT_B 1
> > @@ -19,14 +20,11 @@
> > #define CLK_MAX_DIV 63
> > #define CLK_SRC_24M (0 << 6)
> > #define CLK_SRC_DIV2 (1 << 6)
> > -#define CLK_CO_PHASE_000 (0 << 8)
> > -#define CLK_CO_PHASE_090 (1 << 8)
> > -#define CLK_CO_PHASE_180 (2 << 8)
> > -#define CLK_CO_PHASE_270 (3 << 8)
> > -#define CLK_TX_PHASE_000 (0 << 10)
> > -#define CLK_TX_PHASE_090 (1 << 10)
> > -#define CLK_TX_PHASE_180 (2 << 10)
> > -#define CLK_TX_PHASE_270 (3 << 10)
> > +
> > +#define CLK_PHASE_180 2
> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> > +
> > #define CLK_ALWAYS_ON BIT(24)
> >
> > #define MESON_SD_EMMC_CFG 0x44
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..ad697d3a5e 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > /* 180 phase core clock */
> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > - /* 180 phase tx clock */
> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> > + meson_mmc_clk |= CLK_PHASE_180;
> > + /* 000 phase rx clock */
> > + meson_mmc_clk |= CLK_RX_PHASE_MASK;
> > + /* 000 phase tx clock */
> > + meson_mmc_clk |= CLK_TX_PHASE_MASK;
>
> The comment on your previous version seemed correct but I think what you
> have implemented here is still not doing what you expect.
Thanks for your review. Ok I admit, I did not study the code correctly and
it's wrong to set this way. Plz discard this changes it's wrong.
It did not worked for some sdcards and emmc.
-Anand
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
2019-12-26 11:33 ` Anand Moon
@ 2019-12-26 11:33 ` Anand Moon
-1 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: Neil Armstrong, Peng Fan, Jerome Brunet, u-boot-amlogic, u-boot
Enable GIC support for G12A/G12B platform.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
include/configs/meson64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 736081277d..50707a3197 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -8,7 +8,7 @@
#define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */
-#if defined(CONFIG_MESON_AXG)
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
#define GICD_BASE 0xffc01000
#define GICC_BASE 0xffc02000
#else /* MESON GXL and GXBB */
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
@ 2019-12-26 11:33 ` Anand Moon
0 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: u-boot
Enable GIC support for G12A/G12B platform.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
include/configs/meson64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 736081277d..50707a3197 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -8,7 +8,7 @@
#define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */
-#if defined(CONFIG_MESON_AXG)
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
#define GICD_BASE 0xffc01000
#define GICC_BASE 0xffc02000
#else /* MESON GXL and GXBB */
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
2019-12-26 11:33 ` Anand Moon
@ 2020-01-07 13:41 ` Neil Armstrong
-1 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2020-01-07 13:41 UTC (permalink / raw)
To: Anand Moon, Peng Fan, Jerome Brunet, u-boot-amlogic, u-boot
On 26/12/2019 12:33, Anand Moon wrote:
> Enable GIC support for G12A/G12B platform.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> include/configs/meson64.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> index 736081277d..50707a3197 100644
> --- a/include/configs/meson64.h
> +++ b/include/configs/meson64.h
> @@ -8,7 +8,7 @@
> #define __MESON64_CONFIG_H
>
> /* Generic Interrupt Controller Definitions */
> -#if defined(CONFIG_MESON_AXG)
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> #define GICD_BASE 0xffc01000
> #define GICC_BASE 0xffc02000
> #else /* MESON GXL and GXBB */
>
Applied this patch to u-boot-amlogic
Neil
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
@ 2020-01-07 13:41 ` Neil Armstrong
0 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2020-01-07 13:41 UTC (permalink / raw)
To: u-boot
On 26/12/2019 12:33, Anand Moon wrote:
> Enable GIC support for G12A/G12B platform.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> include/configs/meson64.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> index 736081277d..50707a3197 100644
> --- a/include/configs/meson64.h
> +++ b/include/configs/meson64.h
> @@ -8,7 +8,7 @@
> #define __MESON64_CONFIG_H
>
> /* Generic Interrupt Controller Definitions */
> -#if defined(CONFIG_MESON_AXG)
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> #define GICD_BASE 0xffc01000
> #define GICC_BASE 0xffc02000
> #else /* MESON GXL and GXBB */
>
Applied this patch to u-boot-amlogic
Neil
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
2020-01-07 13:41 ` Neil Armstrong
@ 2020-01-08 1:15 ` Peng Fan
-1 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2020-01-08 1:15 UTC (permalink / raw)
To: Neil Armstrong, Anand Moon, Jerome Brunet,
u-boot-amlogic@groups.io, u-boot@lists.denx.de
> Subject: Re: [PATCHv3 2/3] configs: meson64: enable GIC support for
> G12A/G12B
>
> On 26/12/2019 12:33, Anand Moon wrote:
> > Enable GIC support for G12A/G12B platform.
Just wonder what is GIC support in U-Boot?
Thanks,
Peng.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> > ---
> > include/configs/meson64.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> > index 736081277d..50707a3197 100644
> > --- a/include/configs/meson64.h
> > +++ b/include/configs/meson64.h
> > @@ -8,7 +8,7 @@
> > #define __MESON64_CONFIG_H
> >
> > /* Generic Interrupt Controller Definitions */ -#if
> > defined(CONFIG_MESON_AXG)
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > #define GICD_BASE 0xffc01000
> > #define GICC_BASE 0xffc02000
> > #else /* MESON GXL and GXBB */
> >
>
> Applied this patch to u-boot-amlogic
>
> Neil
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 2/3] configs: meson64: enable GIC support for G12A/G12B
@ 2020-01-08 1:15 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2020-01-08 1:15 UTC (permalink / raw)
To: u-boot
> Subject: Re: [PATCHv3 2/3] configs: meson64: enable GIC support for
> G12A/G12B
>
> On 26/12/2019 12:33, Anand Moon wrote:
> > Enable GIC support for G12A/G12B platform.
Just wonder what is GIC support in U-Boot?
Thanks,
Peng.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> > ---
> > include/configs/meson64.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> > index 736081277d..50707a3197 100644
> > --- a/include/configs/meson64.h
> > +++ b/include/configs/meson64.h
> > @@ -8,7 +8,7 @@
> > #define __MESON64_CONFIG_H
> >
> > /* Generic Interrupt Controller Definitions */ -#if
> > defined(CONFIG_MESON_AXG)
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > #define GICD_BASE 0xffc01000
> > #define GICC_BASE 0xffc02000
> > #else /* MESON GXL and GXBB */
> >
>
> Applied this patch to u-boot-amlogic
>
> Neil
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCHv3 3/3] board: amlogic: select PWRSEQ for all amlogic platform
2019-12-26 11:33 ` Anand Moon
@ 2019-12-26 11:33 ` Anand Moon
-1 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: Neil Armstrong, Peng Fan, Jerome Brunet, u-boot-amlogic, u-boot
commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
introduce CONFIG_PWESEQ for power sequence for eMMC module on
amlogic platform, so enable this to all amlogic boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/mach-meson/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index e29e4c0acc..513a33dae2 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,6 +8,7 @@ config MESON64_COMMON
select DM_SERIAL
select SYSCON
select REGMAP
+ select PWRSEQ
select BOARD_LATE_INIT
imply CMD_DM
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCHv3 3/3] board: amlogic: select PWRSEQ for all amlogic platform
@ 2019-12-26 11:33 ` Anand Moon
0 siblings, 0 replies; 18+ messages in thread
From: Anand Moon @ 2019-12-26 11:33 UTC (permalink / raw)
To: u-boot
commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
introduce CONFIG_PWESEQ for power sequence for eMMC module on
amlogic platform, so enable this to all amlogic boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/mach-meson/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index e29e4c0acc..513a33dae2 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,6 +8,7 @@ config MESON64_COMMON
select DM_SERIAL
select SYSCON
select REGMAP
+ select PWRSEQ
select BOARD_LATE_INIT
imply CMD_DM
--
2.24.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCHv3 3/3] board: amlogic: select PWRSEQ for all amlogic platform
2019-12-26 11:33 ` Anand Moon
@ 2020-01-07 13:42 ` Neil Armstrong
-1 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2020-01-07 13:42 UTC (permalink / raw)
To: Anand Moon, Peng Fan, Jerome Brunet, u-boot-amlogic, u-boot
On 26/12/2019 12:33, Anand Moon wrote:
> commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
> introduce CONFIG_PWESEQ for power sequence for eMMC module on
> amlogic platform, so enable this to all amlogic boards.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm/mach-meson/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index e29e4c0acc..513a33dae2 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -8,6 +8,7 @@ config MESON64_COMMON
> select DM_SERIAL
> select SYSCON
> select REGMAP
> + select PWRSEQ
> select BOARD_LATE_INIT
> imply CMD_DM
>
>
Applied this patch to u-boot-amlogic
Neil
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCHv3 3/3] board: amlogic: select PWRSEQ for all amlogic platform
@ 2020-01-07 13:42 ` Neil Armstrong
0 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2020-01-07 13:42 UTC (permalink / raw)
To: u-boot
On 26/12/2019 12:33, Anand Moon wrote:
> commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
> introduce CONFIG_PWESEQ for power sequence for eMMC module on
> amlogic platform, so enable this to all amlogic boards.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm/mach-meson/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index e29e4c0acc..513a33dae2 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -8,6 +8,7 @@ config MESON64_COMMON
> select DM_SERIAL
> select SYSCON
> select REGMAP
> + select PWRSEQ
> select BOARD_LATE_INIT
> imply CMD_DM
>
>
Applied this patch to u-boot-amlogic
Neil
^ permalink raw reply [flat|nested] 18+ messages in thread