From: Andrew Lunn <andrew@lunn.ch>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: f.fainelli@gmail.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
davem@davemloft.net, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/1] net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs
Date: Thu, 26 Dec 2019 22:36:14 +0100 [thread overview]
Message-ID: <20191226213614.GC32477@lunn.ch> (raw)
In-Reply-To: <20191226190101.3766479-2-martin.blumenstingl@googlemail.com>
On Thu, Dec 26, 2019 at 08:01:01PM +0100, Martin Blumenstingl wrote:
> GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for
> the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate
> can be adjusted at runtime.
>
> So far we have been running MPLL2 with ~250MHz (and the internal
> m250_div with value 1), which worked enough that we could transfer data
> with an TX delay of 4ns. Unfortunately there is high packet loss with
> an RGMII PHY when transferring data (receiving data works fine though).
> Odroid-C1's u-boot is running with a TX delay of only 2ns as well as
> the internal m250_div set to 2 - no lost (TX) packets can be observed
> with that setting in u-boot.
>
> Manual testing has shown that the TX packet loss goes away when using
> the following settings in Linux (the vendor kernel uses the same
> settings):
> - MPLL2 clock set to ~500MHz
> - m250_div set to 2
> - TX delay set to 2ns on the MAC side
>
> Update the m250_div divider settings to only accept dividers greater or
> equal 2 to fix the TX delay generated by the MAC.
>
> iperf3 results before the change:
> [ ID] Interval Transfer Bitrate Retr
> [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender
> [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver
>
> iperf3 results after the change (including an updated TX delay of 2ns):
> [ ID] Interval Transfer Bitrate Retr Cwnd
> [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender
> [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver
>
> Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: f.fainelli@gmail.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
davem@davemloft.net, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/1] net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs
Date: Thu, 26 Dec 2019 22:36:14 +0100 [thread overview]
Message-ID: <20191226213614.GC32477@lunn.ch> (raw)
In-Reply-To: <20191226190101.3766479-2-martin.blumenstingl@googlemail.com>
On Thu, Dec 26, 2019 at 08:01:01PM +0100, Martin Blumenstingl wrote:
> GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for
> the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate
> can be adjusted at runtime.
>
> So far we have been running MPLL2 with ~250MHz (and the internal
> m250_div with value 1), which worked enough that we could transfer data
> with an TX delay of 4ns. Unfortunately there is high packet loss with
> an RGMII PHY when transferring data (receiving data works fine though).
> Odroid-C1's u-boot is running with a TX delay of only 2ns as well as
> the internal m250_div set to 2 - no lost (TX) packets can be observed
> with that setting in u-boot.
>
> Manual testing has shown that the TX packet loss goes away when using
> the following settings in Linux (the vendor kernel uses the same
> settings):
> - MPLL2 clock set to ~500MHz
> - m250_div set to 2
> - TX delay set to 2ns on the MAC side
>
> Update the m250_div divider settings to only accept dividers greater or
> equal 2 to fix the TX delay generated by the MAC.
>
> iperf3 results before the change:
> [ ID] Interval Transfer Bitrate Retr
> [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender
> [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver
>
> iperf3 results after the change (including an updated TX delay of 2ns):
> [ ID] Interval Transfer Bitrate Retr Cwnd
> [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender
> [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver
>
> Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: f.fainelli@gmail.com, davem@davemloft.net,
netdev@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/1] net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs
Date: Thu, 26 Dec 2019 22:36:14 +0100 [thread overview]
Message-ID: <20191226213614.GC32477@lunn.ch> (raw)
In-Reply-To: <20191226190101.3766479-2-martin.blumenstingl@googlemail.com>
On Thu, Dec 26, 2019 at 08:01:01PM +0100, Martin Blumenstingl wrote:
> GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for
> the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate
> can be adjusted at runtime.
>
> So far we have been running MPLL2 with ~250MHz (and the internal
> m250_div with value 1), which worked enough that we could transfer data
> with an TX delay of 4ns. Unfortunately there is high packet loss with
> an RGMII PHY when transferring data (receiving data works fine though).
> Odroid-C1's u-boot is running with a TX delay of only 2ns as well as
> the internal m250_div set to 2 - no lost (TX) packets can be observed
> with that setting in u-boot.
>
> Manual testing has shown that the TX packet loss goes away when using
> the following settings in Linux (the vendor kernel uses the same
> settings):
> - MPLL2 clock set to ~500MHz
> - m250_div set to 2
> - TX delay set to 2ns on the MAC side
>
> Update the m250_div divider settings to only accept dividers greater or
> equal 2 to fix the TX delay generated by the MAC.
>
> iperf3 results before the change:
> [ ID] Interval Transfer Bitrate Retr
> [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender
> [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver
>
> iperf3 results after the change (including an updated TX delay of 2ns):
> [ ID] Interval Transfer Bitrate Retr Cwnd
> [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender
> [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver
>
> Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2019-12-26 21:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-26 19:01 [PATCH v2 0/1] dwmac-meson8b: Ethernet RGMII TX delay fix Martin Blumenstingl
2019-12-26 19:01 ` Martin Blumenstingl
2019-12-26 19:01 ` Martin Blumenstingl
2019-12-26 19:01 ` [PATCH v2 1/1] net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs Martin Blumenstingl
2019-12-26 19:01 ` Martin Blumenstingl
2019-12-26 19:01 ` Martin Blumenstingl
2019-12-26 21:36 ` Andrew Lunn [this message]
2019-12-26 21:36 ` Andrew Lunn
2019-12-26 21:36 ` Andrew Lunn
2019-12-28 0:37 ` David Miller
2019-12-28 0:37 ` David Miller
2019-12-28 0:37 ` David Miller
2020-01-09 18:21 ` [PATCH v2 0/1] dwmac-meson8b: Ethernet RGMII TX delay fix patchwork-bot+linux-amlogic
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