From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Andrew Murray <andrew.murray@arm.com>,
Tom Joseph <tjoseph@cadence.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
<linux-doc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-rockchip@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions
Date: Tue, 31 Dec 2019 17:05:29 +0530 [thread overview]
Message-ID: <20191231113534.30405-3-kishon@ti.com> (raw)
In-Reply-To: <20191231113534.30405-1-kishon@ti.com>
Add binding to specify maximum number of virtual functions that can be
associated with each physical function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 2 ++
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 4a0475e2ba7e..432578202733 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
Optional properties:
- max-functions: Maximum number of functions that can be configured (default 1).
+- max-virtual-functions: Maximum number of virtual functions that can be
+ associated with each physical function.
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
than one in the list. If only one PHY listed it must manage all lanes.
- phy-names: List of names to identify the PHY.
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 4621c62016c7..1d4964ba494f 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -61,6 +61,12 @@ properties:
minimum: 1
maximum: 6
+ max-virtual-functions:
+ minItems: 1
+ maxItems: 6
+ description: As defined in
+ Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+
dma-coherent:
description: Indicates that the PCIe IP block can ensure the coherency
@@ -85,6 +91,7 @@ required:
- cdns,max-outbound-regions
- dma-coherent
- max-functions
+ - max-virtual-functions
- phys
- phy-names
@@ -107,6 +114,7 @@ examples:
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Andrew Murray <andrew.murray@arm.com>,
Tom Joseph <tjoseph@cadence.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Jonathan Corbet <corbet@lwn.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions
Date: Tue, 31 Dec 2019 17:05:29 +0530 [thread overview]
Message-ID: <20191231113534.30405-3-kishon@ti.com> (raw)
In-Reply-To: <20191231113534.30405-1-kishon@ti.com>
Add binding to specify maximum number of virtual functions that can be
associated with each physical function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 2 ++
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 4a0475e2ba7e..432578202733 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
Optional properties:
- max-functions: Maximum number of functions that can be configured (default 1).
+- max-virtual-functions: Maximum number of virtual functions that can be
+ associated with each physical function.
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
than one in the list. If only one PHY listed it must manage all lanes.
- phy-names: List of names to identify the PHY.
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 4621c62016c7..1d4964ba494f 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -61,6 +61,12 @@ properties:
minimum: 1
maximum: 6
+ max-virtual-functions:
+ minItems: 1
+ maxItems: 6
+ description: As defined in
+ Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+
dma-coherent:
description: Indicates that the PCIe IP block can ensure the coherency
@@ -85,6 +91,7 @@ required:
- cdns,max-outbound-regions
- dma-coherent
- max-functions
+ - max-virtual-functions
- phys
- phy-names
@@ -107,6 +114,7 @@ examples:
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Andrew Murray <andrew.murray@arm.com>,
Tom Joseph <tjoseph@cadence.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-pci@vger.kernel.org, Jonathan Corbet <corbet@lwn.net>,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions
Date: Tue, 31 Dec 2019 17:05:29 +0530 [thread overview]
Message-ID: <20191231113534.30405-3-kishon@ti.com> (raw)
In-Reply-To: <20191231113534.30405-1-kishon@ti.com>
Add binding to specify maximum number of virtual functions that can be
associated with each physical function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 2 ++
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 4a0475e2ba7e..432578202733 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
Optional properties:
- max-functions: Maximum number of functions that can be configured (default 1).
+- max-virtual-functions: Maximum number of virtual functions that can be
+ associated with each physical function.
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
than one in the list. If only one PHY listed it must manage all lanes.
- phy-names: List of names to identify the PHY.
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 4621c62016c7..1d4964ba494f 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -61,6 +61,12 @@ properties:
minimum: 1
maximum: 6
+ max-virtual-functions:
+ minItems: 1
+ maxItems: 6
+ description: As defined in
+ Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+
dma-coherent:
description: Indicates that the PCIe IP block can ensure the coherency
@@ -85,6 +91,7 @@ required:
- cdns,max-outbound-regions
- dma-coherent
- max-functions
+ - max-virtual-functions
- phys
- phy-names
@@ -107,6 +114,7 @@ examples:
clock-names = "fck";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-12-31 11:34 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-31 11:35 [PATCH 0/7] Add SR-IOV support in PCIe Endpoint Core Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 1/7] Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I [this message]
2019-12-31 11:35 ` [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2020-01-15 1:40 ` Rob Herring
2020-01-15 1:40 ` Rob Herring
2020-01-16 11:29 ` Kishon Vijay Abraham I
2020-01-16 11:29 ` Kishon Vijay Abraham I
2020-01-16 11:29 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 3/7] PCI: endpoint: Add support to add virtual function in endpoint core Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 4/7] PCI: endpoint: Add support to link a physical function to a virtual function Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 5/7] PCI: endpoint: Add virtual function number in pci_epc ops Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 6/7] PCI: cadence: Add support to configure virtual functions Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` [PATCH 7/7] misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
2019-12-31 11:35 ` Kishon Vijay Abraham I
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