From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 16/22] iommu/vt-d: Setup pasid entries for iova over first level
Date: Thu, 2 Jan 2020 08:18:17 +0800 [thread overview]
Message-ID: <20200102001823.21976-17-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200102001823.21976-1-baolu.lu@linux.intel.com>
Intel VT-d in scalable mode supports two types of page tables for
IOVA translation: first level and second level. The IOMMU driver
can choose one from both for IOVA translation according to the use
case. This sets up the pasid entry if a domain is selected to use
the first-level page table for iova translation.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel-iommu.c | 57 +++++++++++++++++++++++++++++++++----
include/linux/intel-iommu.h | 16 +++++++----
2 files changed, 62 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 35f65628202c..071cbc172ce8 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -571,6 +571,11 @@ static inline int domain_type_is_si(struct dmar_domain *domain)
return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY;
}
+static inline bool domain_use_first_level(struct dmar_domain *domain)
+{
+ return domain->flags & DOMAIN_FLAG_USE_FIRST_LEVEL;
+}
+
static inline int domain_pfn_supported(struct dmar_domain *domain,
unsigned long pfn)
{
@@ -932,6 +937,8 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
+ if (domain_use_first_level(domain))
+ pteval |= DMA_FL_PTE_XD;
if (cmpxchg64(&pte->val, 0ULL, pteval))
/* Someone else set it while we were thinking; use theirs. */
free_pgtable_page(tmp_page);
@@ -2281,17 +2288,20 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
unsigned long sg_res = 0;
unsigned int largepage_lvl = 0;
unsigned long lvl_pages = 0;
+ u64 attr;
BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
return -EINVAL;
- prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
+ attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);
+ if (domain_use_first_level(domain))
+ attr |= DMA_FL_PTE_PRESENT | DMA_FL_PTE_XD;
if (!sg) {
sg_res = nr_pages;
- pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
+ pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr;
}
while (nr_pages > 0) {
@@ -2303,7 +2313,7 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
sg_res = aligned_nrpages(sg->offset, sg->length);
sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + pgoff;
sg->dma_length = sg->length;
- pteval = (sg_phys(sg) - pgoff) | prot;
+ pteval = (sg_phys(sg) - pgoff) | attr;
phys_pfn = pteval >> VTD_PAGE_SHIFT;
}
@@ -2515,6 +2525,36 @@ dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
return NULL;
}
+static int domain_setup_first_level(struct intel_iommu *iommu,
+ struct dmar_domain *domain,
+ struct device *dev,
+ int pasid)
+{
+ int flags = PASID_FLAG_SUPERVISOR_MODE;
+ struct dma_pte *pgd = domain->pgd;
+ int agaw, level;
+
+ /*
+ * Skip top levels of page tables for iommu which has
+ * less agaw than default. Unnecessary for PT mode.
+ */
+ for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
+ pgd = phys_to_virt(dma_pte_addr(pgd));
+ if (!dma_pte_present(pgd))
+ return -ENOMEM;
+ }
+
+ level = agaw_to_level(agaw);
+ if (level != 4 && level != 5)
+ return -EINVAL;
+
+ flags |= (level == 5) ? PASID_FLAG_FL5LP : 0;
+
+ return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
+ domain->iommu_did[iommu->seq_id],
+ flags);
+}
+
static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
int bus, int devfn,
struct device *dev,
@@ -2614,6 +2654,9 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
if (hw_pass_through && domain_type_is_si(domain))
ret = intel_pasid_setup_pass_through(iommu, domain,
dev, PASID_RID2PASID);
+ else if (domain_use_first_level(domain))
+ ret = domain_setup_first_level(iommu, domain, dev,
+ PASID_RID2PASID);
else
ret = intel_pasid_setup_second_level(iommu, domain,
dev, PASID_RID2PASID);
@@ -5374,8 +5417,12 @@ static int aux_domain_add_dev(struct dmar_domain *domain,
goto attach_failed;
/* Setup the PASID entry for mediated devices: */
- ret = intel_pasid_setup_second_level(iommu, domain, dev,
- domain->default_pasid);
+ if (domain_use_first_level(domain))
+ ret = domain_setup_first_level(iommu, domain, dev,
+ domain->default_pasid);
+ else
+ ret = intel_pasid_setup_second_level(iommu, domain, dev,
+ domain->default_pasid);
if (ret)
goto table_failed;
spin_unlock(&iommu->lock);
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index aaece25c055f..454c69712131 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -34,10 +34,13 @@
#define VTD_STRIDE_SHIFT (9)
#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
-#define DMA_PTE_READ (1)
-#define DMA_PTE_WRITE (2)
-#define DMA_PTE_LARGE_PAGE (1 << 7)
-#define DMA_PTE_SNP (1 << 11)
+#define DMA_PTE_READ BIT_ULL(0)
+#define DMA_PTE_WRITE BIT_ULL(1)
+#define DMA_PTE_LARGE_PAGE BIT_ULL(7)
+#define DMA_PTE_SNP BIT_ULL(11)
+
+#define DMA_FL_PTE_PRESENT BIT_ULL(0)
+#define DMA_FL_PTE_XD BIT_ULL(63)
#define CONTEXT_TT_MULTI_LEVEL 0
#define CONTEXT_TT_DEV_IOTLB 1
@@ -610,10 +613,11 @@ static inline void dma_clear_pte(struct dma_pte *pte)
static inline u64 dma_pte_addr(struct dma_pte *pte)
{
#ifdef CONFIG_64BIT
- return pte->val & VTD_PAGE_MASK;
+ return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
#else
/* Must have a full atomic 64-bit read */
- return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+ return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
+ VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
#endif
}
--
2.17.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-01-02 0:19 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 0:18 [PULL REQUEST] iommu/vt-d: patches for v5.6 Lu Baolu
2020-01-02 0:18 ` [PATCH 01/22] iommu/vt-d: Add Kconfig option to enable/disable scalable mode Lu Baolu
2020-01-02 0:18 ` [PATCH 02/22] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks Lu Baolu
2020-01-02 0:18 ` [PATCH 03/22] iommu/vt-d: Match CPU and IOMMU paging mode Lu Baolu
2020-01-02 0:18 ` [PATCH 04/22] iommu/vt-d: Reject SVM bind for failed capability check Lu Baolu
2020-01-02 0:18 ` [PATCH 05/22] iommu/vt-d: Avoid duplicated code for PASID setup Lu Baolu
2020-01-02 0:18 ` [PATCH 06/22] iommu/vt-d: Fix off-by-one in PASID allocation Lu Baolu
2020-01-02 0:18 ` [PATCH 07/22] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Lu Baolu
2020-01-02 0:18 ` [PATCH 08/22] iommu/vt-d: Avoid sending invalid page response Lu Baolu
2020-01-02 0:18 ` [PATCH 09/22] iommu/vt-d: Misc macro clean up for SVM Lu Baolu
2020-01-02 0:18 ` [PATCH 10/22] iommu/vt-d: trace: Extend map_sg trace event Lu Baolu
2020-01-02 0:18 ` [PATCH 11/22] iommu/vt-d: Avoid iova flush queue in strict mode Lu Baolu
2020-01-02 0:18 ` [PATCH 12/22] iommu/vt-d: Loose requirement for flush queue initializaton Lu Baolu
2020-01-02 0:18 ` [PATCH 13/22] iommu/vt-d: Identify domains using first level page table Lu Baolu
2020-01-02 0:18 ` [PATCH 14/22] iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr Lu Baolu
2020-01-02 0:18 ` [PATCH 15/22] iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup Lu Baolu
2020-01-02 0:18 ` Lu Baolu [this message]
2020-01-02 0:18 ` [PATCH 17/22] iommu/vt-d: Flush PASID-based iotlb for iova over first level Lu Baolu
2020-01-02 0:18 ` [PATCH 18/22] iommu/vt-d: Make first level IOVA canonical Lu Baolu
2020-01-02 0:18 ` [PATCH 19/22] iommu/vt-d: Update first level super page capability Lu Baolu
2020-01-02 0:18 ` [PATCH 20/22] iommu/vt-d: Use iova over first level Lu Baolu
2020-01-02 0:18 ` [PATCH 21/22] iommu/vt-d: debugfs: Add support to show page table internals Lu Baolu
2020-01-02 0:18 ` [PATCH 22/22] iommu/vt-d: Add a quirk flag for scope mismatched devices Lu Baolu
2020-01-02 2:11 ` Roland Dreier via iommu
2020-01-02 2:14 ` Lu Baolu
2020-01-02 2:25 ` Roland Dreier via iommu
2020-01-02 2:34 ` Lu Baolu
2020-01-03 0:32 ` Lu Baolu
2020-01-04 16:52 ` Roland Dreier via iommu
2020-01-05 3:43 ` Lu Baolu
2020-01-06 17:05 ` Jerry Snitselaar
2020-01-07 0:35 ` Lu Baolu
2020-01-07 1:30 ` Jerry Snitselaar
2020-01-07 1:47 ` Lu Baolu
2020-01-09 0:12 ` Roland Dreier via iommu
2020-01-08 14:16 ` Christoph Hellwig
2020-01-08 23:28 ` Lu Baolu
2020-01-09 7:06 ` Christoph Hellwig
2020-01-09 8:53 ` Lu Baolu
2020-01-09 8:56 ` 答复: " Jim,Yan
2020-01-07 13:06 ` [PULL REQUEST] iommu/vt-d: patches for v5.6 Joerg Roedel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200102001823.21976-17-baolu.lu@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.