All of lore.kernel.org
 help / color / mirror / Atom feed
From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, Anup.Patel@wdc.com,
	vincent.chen@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, bmeng.cn@gmail.com, atish.patra@wdc.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	arnd@arndb.de, linux-csky@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <ren_guo@c-sky.com>
Subject: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset
Date: Sun,  5 Jan 2020 10:52:14 +0800	[thread overview]
Message-ID: <20200105025215.2522-1-guoren@kernel.org> (raw)

From: Guo Ren <ren_guo@c-sky.com>

CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_msia register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
---
 arch/riscv/kernel/head.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 797802c73dee..2227db63f895 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -251,7 +251,7 @@ ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	bnez	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
-- 
2.17.0

WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, Anup.Patel@wdc.com,
	vincent.chen@sifive.com, zong.li@sifive.com,
	greentime.hu@sifive.com, bmeng.cn@gmail.com, atish.patra@wdc.com
Cc: linux-arch@vger.kernel.org, arnd@arndb.de,
	linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
	Guo Ren <ren_guo@c-sky.com>,
	linux-riscv@lists.infradead.org
Subject: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset
Date: Sun,  5 Jan 2020 10:52:14 +0800	[thread overview]
Message-ID: <20200105025215.2522-1-guoren@kernel.org> (raw)

From: Guo Ren <ren_guo@c-sky.com>

CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_msia register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
---
 arch/riscv/kernel/head.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 797802c73dee..2227db63f895 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -251,7 +251,7 @@ ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	bnez	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
-- 
2.17.0



             reply	other threads:[~2020-01-05  2:52 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-05  2:52 guoren [this message]
2020-01-05  2:52 ` [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset guoren
2020-01-05  2:52 ` [PATCH 2/2] riscv: Add vector ISA support guoren
2020-01-05  2:52   ` guoren
2020-01-05  8:39   ` Andreas Schwab
2020-01-05  8:39     ` Andreas Schwab
2020-01-05  9:01     ` Guo Ren
2020-01-05  9:01       ` Guo Ren
2020-01-05 12:32   ` kbuild test robot
2020-01-05 12:32     ` kbuild test robot
2020-01-05 12:32     ` kbuild test robot
2020-01-06  3:27     ` Guo Ren
2020-01-06  3:27       ` Guo Ren
2020-01-06  3:27       ` Guo Ren
2020-01-05 16:22   ` kbuild test robot
2020-01-05 16:22     ` kbuild test robot
2020-01-05 16:22     ` kbuild test robot
2020-01-06  2:45   ` Alan Kao
2020-01-06  2:45     ` Alan Kao
2020-01-06  2:45     ` Alan Kao
2020-01-06  3:00     ` Anup Patel
2020-01-06  3:00       ` Anup Patel
2020-01-06  3:38       ` Guo Ren
2020-01-06  3:38         ` Guo Ren
2020-01-06  3:32     ` Guo Ren
2020-01-06  3:32       ` Guo Ren
2020-01-06  9:25   ` Anup Patel
2020-01-06  9:25     ` Anup Patel
2020-01-07 16:15     ` Guo Ren
2020-01-07 16:15       ` Guo Ren
2020-01-11  1:30 ` [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset Paul Walmsley
2020-01-11  1:30   ` Paul Walmsley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200105025215.2522-1-guoren@kernel.org \
    --to=guoren@kernel.org \
    --cc=Anup.Patel@wdc.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=arnd@arndb.de \
    --cc=atish.patra@wdc.com \
    --cc=bmeng.cn@gmail.com \
    --cc=greentime.hu@sifive.com \
    --cc=linux-arch@vger.kernel.org \
    --cc=linux-csky@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=ren_guo@c-sky.com \
    --cc=vincent.chen@sifive.com \
    --cc=zong.li@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.