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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Andrew Murray <andrew.murray@arm.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v2 03/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro
Date: Mon, 6 Jan 2020 15:50:47 +0530	[thread overview]
Message-ID: <20200106102058.19183-4-kishon@ti.com> (raw)
In-Reply-To: <20200106102058.19183-1-kishon@ti.com>

Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 include/linux/kernel.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 3adcb39fa6f5..888ad70a80aa 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -34,6 +34,7 @@
 #define ALIGN_DOWN(x, a)	__ALIGN_KERNEL((x) - ((a) - 1), (a))
 #define __ALIGN_MASK(x, mask)	__ALIGN_KERNEL_MASK((x), (mask))
 #define PTR_ALIGN(p, a)		((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define PTR_ALIGN_DOWN(p, a)	((typeof(p))ALIGN_DOWN((unsigned long)(p), (a)))
 #define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
 
 /* generic data direction definitions */
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Andrew Murray <andrew.murray@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v2 03/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro
Date: Mon, 6 Jan 2020 15:50:47 +0530	[thread overview]
Message-ID: <20200106102058.19183-4-kishon@ti.com> (raw)
In-Reply-To: <20200106102058.19183-1-kishon@ti.com>

Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 include/linux/kernel.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 3adcb39fa6f5..888ad70a80aa 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -34,6 +34,7 @@
 #define ALIGN_DOWN(x, a)	__ALIGN_KERNEL((x) - ((a) - 1), (a))
 #define __ALIGN_MASK(x, mask)	__ALIGN_KERNEL_MASK((x), (mask))
 #define PTR_ALIGN(p, a)		((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define PTR_ALIGN_DOWN(p, a)	((typeof(p))ALIGN_DOWN((unsigned long)(p), (a)))
 #define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
 
 /* generic data direction definitions */
-- 
2.17.1


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  parent reply	other threads:[~2020-01-06 10:19 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-06 10:20 [PATCH v2 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20 ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 01/14] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-08  3:43   ` Rob Herring
2020-01-08  3:43     ` Rob Herring
2020-01-08  5:35     ` Kishon Vijay Abraham I
2020-01-08  5:35       ` Kishon Vijay Abraham I
2020-01-16 11:31       ` Kishon Vijay Abraham I
2020-01-16 11:31         ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 02/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` Kishon Vijay Abraham I [this message]
2020-01-06 10:20   ` [PATCH v2 03/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 04/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 05/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 06/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 07/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 08/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 09/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-01-06 10:20   ` Kishon Vijay Abraham I

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