All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH] drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms
@ 2019-12-30 23:45 Matt Roper
  2019-12-31  0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Matt Roper @ 2019-12-30 23:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

The bits in DDI_BUF_CTL related to DP vswing emphasis were removed on
GLK since the relevant programming has moved to the PHY registers.  The
bits still exist on BXT, but have a programming note indicating that
they're ignored.  Let's stop programming them on gen9lp and and gen10+.

Bspec: 7534
Bspec: 49533
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3a538789c585..c63a1712515c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1148,6 +1148,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
 	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
+		u32 tmp;
+
 		/* Configure DP_TP_CTL with auto-training */
 		I915_WRITE(DP_TP_CTL(PORT_E),
 					DP_TP_CTL_FDI_AUTOTRAIN |
@@ -1159,10 +1161,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		 * DDI E does not support port reversal, the functionality is
 		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 		 * port reversal bit */
-		I915_WRITE(DDI_BUF_CTL(PORT_E),
-			   DDI_BUF_CTL_ENABLE |
-			   ((crtc_state->fdi_lanes - 1) << 1) |
-			   DDI_BUF_TRANS_SELECT(i / 2));
+		tmp = DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1);
+		if (INTEL_GEN(dev_priv) <= 9 && !IS_GEN9_LP(dev_priv))
+			tmp |= DDI_BUF_TRANS_SELECT(i / 2);
+		I915_WRITE(DDI_BUF_CTL(PORT_E), tmp);
 		POSTING_READ(DDI_BUF_CTL(PORT_E));
 
 		udelay(600);
@@ -1238,13 +1240,16 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 
 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *intel_dig_port =
 		enc_to_dig_port(&encoder->base);
 
-	intel_dp->DP = intel_dig_port->saved_port_bits |
-		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
+	intel_dp->DP = intel_dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
 	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+	if (INTEL_GEN(dev_priv) <= 9 && !IS_GEN9_LP(dev_priv))
+		intel_dp->DP |= DDI_BUF_TRANS_SELECT(0);
+
 }
 
 static struct intel_encoder *
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-01-07 18:46 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-12-30 23:45 [Intel-gfx] [PATCH] drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms Matt Roper
2019-12-31  0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2019-12-31 10:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-01-07 18:46 ` [Intel-gfx] [PATCH] " Ville Syrjälä

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.