Re: [PATCH net-next v5 09/15] net: phy: mscc: macsec support

[kbuild test robot <lkp@intel.com>]

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Hi Antoine,

I love your patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]
[also build test WARNING on net/master linus/master v5.5-rc5 next-20200110]
[cannot apply to sparc-next/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Antoine-Tenart/net-macsec-initial-support-for-hardware-offloading/20200111-075835
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 4a4a52d49d11f5c4a0df8b9806c8c5563801f753
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.1-129-g341daf20-dirty
        make ARCH=x86_64 allmodconfig
        make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)

>> drivers/net/phy/mscc.c:2036:42: sparse: sparse: cast from restricted sci_t
>> drivers/net/phy/mscc.c:2038:42: sparse: sparse: restricted sci_t degrades to integer
>> drivers/net/phy/mscc.c:2045:42: sparse: sparse: restricted __be16 degrades to integer
   drivers/net/phy/mscc.c:2251:34: sparse: sparse: cast from restricted sci_t
   drivers/net/phy/mscc.c:2253:34: sparse: sparse: restricted sci_t degrades to integer

vim +2036 drivers/net/phy/mscc.c

  2012	
  2013	static void vsc8584_macsec_flow(struct phy_device *phydev,
  2014					struct macsec_flow *flow)
  2015	{
  2016		struct vsc8531_private *priv = phydev->priv;
  2017		enum macsec_bank bank = flow->bank;
  2018		u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
  2019	
  2020		if (flow->match.tagged)
  2021			match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
  2022		if (flow->match.untagged)
  2023			match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
  2024	
  2025		if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
  2026			match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
  2027			mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
  2028		}
  2029	
  2030		if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
  2031			match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
  2032			mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
  2033				MSCC_MS_SAM_MASK_SCI_MASK;
  2034	
  2035			vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
> 2036						 lower_32_bits(flow->rx_sa->sc->sci));
  2037			vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
> 2038						 upper_32_bits(flow->rx_sa->sc->sci));
  2039		}
  2040	
  2041		if (flow->match.etype) {
  2042			mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
  2043	
  2044			vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
> 2045						 MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype)));
  2046		}
  2047	
  2048		match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
  2049	
  2050		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
  2051		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
  2052	
  2053		/* Action for matching packets */
  2054		if (flow->action.drop)
  2055			action = MSCC_MS_FLOW_DROP;
  2056		else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
  2057			action = MSCC_MS_FLOW_BYPASS;
  2058		else
  2059			action = (bank == MACSEC_INGR) ?
  2060				 MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
  2061	
  2062		val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
  2063		      MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
  2064		      MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
  2065	
  2066		if (action == MSCC_MS_FLOW_BYPASS)
  2067			goto write_ctrl;
  2068	
  2069		if (bank == MACSEC_INGR) {
  2070			if (priv->secy->replay_protect)
  2071				val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
  2072			if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
  2073				val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
  2074			else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
  2075				val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
  2076		} else if (bank == MACSEC_EGR) {
  2077			if (priv->secy->protect_frames)
  2078				val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
  2079			if (priv->secy->tx_sc.encrypt)
  2080				val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
  2081			if (priv->secy->tx_sc.send_sci)
  2082				val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
  2083		}
  2084	
  2085	write_ctrl:
  2086		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
  2087	}
  2088	

---
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