From: Stephen Boyd <sboyd@kernel.org>
To: frankc@nvidia.com, hverkuil@xs4all.nl, jonathanh@nvidia.com,
skomatineni@nvidia.com, thierry.reding@gmail.com
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate
Date: Wed, 05 Feb 2020 11:23:41 -0800 [thread overview]
Message-ID: <20200205192341.E4E482072B@mail.kernel.org> (raw)
In-Reply-To: <1580235801-4129-3-git-send-email-skomatineni@nvidia.com>
Quoting Sowjanya Komatineni (2020-01-28 10:23:18)
> Tegra210 CSI hardware internally uses PLLD for internal test pattern
> generator logic.
>
> PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
> out to CSI during TPG mode.
>
> This patch adds this CSI TPG clock gate to Tegra210 clock driver
> to allow Tegra video driver to ungate CSI TPG clock during TPG mode
> and gate during non TPG mode.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: frankc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org,
jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate
Date: Wed, 05 Feb 2020 11:23:41 -0800 [thread overview]
Message-ID: <20200205192341.E4E482072B@mail.kernel.org> (raw)
In-Reply-To: <1580235801-4129-3-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Quoting Sowjanya Komatineni (2020-01-28 10:23:18)
> Tegra210 CSI hardware internally uses PLLD for internal test pattern
> generator logic.
>
> PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
> out to CSI during TPG mode.
>
> This patch adds this CSI TPG clock gate to Tegra210 clock driver
> to allow Tegra video driver to ungate CSI TPG clock during TPG mode
> and gate during non TPG mode.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
Acked-by: Stephen Boyd <sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
next prev parent reply other threads:[~2020-02-05 19:23 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 18:23 [RFC PATCH v1 0/5] Add Tegra driver for video capture Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-01-28 18:23 ` [RFC PATCH v1 1/5] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-02-05 19:23 ` Stephen Boyd
2020-01-28 18:23 ` [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-02-05 19:23 ` Stephen Boyd [this message]
2020-02-05 19:23 ` Stephen Boyd
2020-01-28 18:23 ` [RFC PATCH v1 3/5] dt-binding: tegra: Add VI and CSI bindings Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-01-28 20:32 ` Helen Koike
2020-01-28 21:04 ` Sowjanya Komatineni
2020-01-28 21:04 ` Sowjanya Komatineni
2020-01-28 18:23 ` [RFC PATCH v1 4/5] media: tegra: Add Tegra Video input driver for Tegra210 Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-01-28 21:45 ` Helen Koike
[not found] ` <3cdea635-a9ca-7b9c-3c99-8f489f4d669a-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2020-01-28 22:13 ` Sowjanya Komatineni
2020-01-28 22:13 ` Sowjanya Komatineni
2020-01-29 0:49 ` Sowjanya Komatineni
2020-01-29 0:49 ` Sowjanya Komatineni
2020-01-29 1:05 ` Helen Koike
2020-01-29 1:05 ` Helen Koike
2020-01-29 2:11 ` Sowjanya Komatineni
2020-01-29 2:11 ` Sowjanya Komatineni
2020-01-29 5:59 ` Sowjanya Komatineni
2020-01-29 5:59 ` Sowjanya Komatineni
2020-01-29 10:31 ` Helen Koike
2020-01-29 10:31 ` Helen Koike
2020-01-29 17:49 ` Sowjanya Komatineni
2020-01-29 17:49 ` Sowjanya Komatineni
2020-01-29 18:15 ` Sowjanya Komatineni
2020-01-29 18:15 ` Sowjanya Komatineni
2020-01-29 18:46 ` Helen Koike
2020-01-29 22:40 ` Sowjanya Komatineni
2020-01-29 22:40 ` Sowjanya Komatineni
2020-01-29 18:29 ` Helen Koike
2020-01-29 18:46 ` Sowjanya Komatineni
2020-01-29 18:46 ` Sowjanya Komatineni
2020-01-29 10:09 ` Thierry Reding
2020-01-29 16:25 ` Sowjanya Komatineni
2020-01-29 16:25 ` Sowjanya Komatineni
2020-01-29 11:13 ` Thierry Reding
2020-01-29 11:13 ` Thierry Reding
2020-01-29 17:23 ` Sowjanya Komatineni
2020-01-29 17:23 ` Sowjanya Komatineni
2020-01-30 12:20 ` Thierry Reding
2020-01-30 17:02 ` Sowjanya Komatineni
2020-01-30 17:02 ` Sowjanya Komatineni
2020-01-29 14:16 ` Hans Verkuil (hansverk)
2020-01-29 17:27 ` Sowjanya Komatineni
2020-01-30 14:45 ` Hans Verkuil
2020-01-30 14:45 ` Hans Verkuil
2020-02-05 19:26 ` Stephen Boyd
2020-02-05 19:54 ` Sowjanya Komatineni
2020-02-05 19:54 ` Sowjanya Komatineni
2020-01-28 18:23 ` [RFC PATCH v1 5/5] arm64: tegra: Add Tegra VI CSI suppport in device tree Sowjanya Komatineni
2020-01-28 18:23 ` Sowjanya Komatineni
2020-01-29 9:46 ` Thierry Reding
2020-01-29 9:46 ` Thierry Reding
2020-01-29 16:22 ` Sowjanya Komatineni
2020-01-29 16:22 ` Sowjanya Komatineni
2020-01-30 12:36 ` Thierry Reding
2020-01-30 12:36 ` Thierry Reding
2020-01-30 17:18 ` Sowjanya Komatineni
2020-01-30 17:18 ` Sowjanya Komatineni
2020-01-30 17:58 ` Thierry Reding
2020-01-30 18:58 ` Sowjanya Komatineni
2020-01-30 18:58 ` Sowjanya Komatineni
2020-01-30 20:18 ` Sowjanya Komatineni
2020-01-30 20:18 ` Sowjanya Komatineni
2020-01-31 2:57 ` Sowjanya Komatineni
2020-01-31 2:57 ` Sowjanya Komatineni
2020-01-30 14:41 ` [RFC PATCH v1 0/5] Add Tegra driver for video capture Hans Verkuil
2020-01-30 15:42 ` Thierry Reding
2020-01-31 14:29 ` Hans Verkuil
2020-01-31 17:03 ` Thierry Reding
2020-01-31 17:37 ` Hans Verkuil
2020-01-31 17:37 ` Hans Verkuil
2020-01-31 20:31 ` Thierry Reding
2020-01-31 20:31 ` Thierry Reding
2020-02-04 9:50 ` Hans Verkuil
2020-01-30 17:20 ` Sowjanya Komatineni
2020-01-30 17:20 ` Sowjanya Komatineni
2020-02-04 12:53 ` Hans Verkuil
2020-02-04 12:53 ` Hans Verkuil
2020-02-04 16:42 ` Sowjanya Komatineni
2020-02-04 16:42 ` Sowjanya Komatineni
2020-02-04 17:22 ` Hans Verkuil
2020-02-04 17:22 ` Hans Verkuil
2020-02-04 19:02 ` Sowjanya Komatineni
2020-02-04 19:02 ` Sowjanya Komatineni
2020-02-05 7:57 ` Hans Verkuil
2020-02-05 7:57 ` Hans Verkuil
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