* [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing
@ 2020-02-08 22:01 Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Split the gen7 rcs flush into phases Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2020-02-08 22:01 UTC (permalink / raw)
To: intel-gfx
Don't immediately write the seqno into the breadcrumb slot, but wait
until we've attempted to flush the writes; that is we need to ensure the
memory is coherent prior to updating the breadcrumb so that any
observers who see the new seqno can proceed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 23 +++++++++++++------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index f70b903a98bc..c99017e3c3c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -446,31 +446,40 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
return cs;
}
-#define GEN7_XCS_WA 32
+#define GEN7_XCS_WA 8
static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{
+ const u32 mi_flush_seqno =
+ MI_FLUSH_DW | MI_INVALIDATE_TLB |
+ MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
int i;
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
- *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
- MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
+ /* Stalling flush before we update the actual breadcrumb */
+ *cs++ = mi_flush_seqno;
+ *cs++ = (I915_GEM_HWS_SEQNO_ADDR + 4) | MI_FLUSH_DW_USE_GTT;
+ *cs++ = rq->fence.seqno;
+
+ /* Write the seqno into the breadcrumb */
+ *cs++ = mi_flush_seqno;
*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
*cs++ = rq->fence.seqno;
+ /* Delay for the seqno to land! */
for (i = 0; i < GEN7_XCS_WA; i++) {
*cs++ = MI_STORE_DWORD_INDEX;
*cs++ = I915_GEM_HWS_SEQNO_ADDR;
*cs++ = rq->fence.seqno;
}
- *cs++ = MI_FLUSH_DW;
- *cs++ = 0;
- *cs++ = 0;
+ /* One final stall! */
+ *cs++ = mi_flush_seqno;
+ *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
+ *cs++ = rq->fence.seqno;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
--
2.25.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: Split the gen7 rcs flush into phases
2020-02-08 22:01 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
@ 2020-02-08 22:01 ` Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt Chris Wilson
2020-02-08 23:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-02-08 22:01 UTC (permalink / raw)
To: intel-gfx
We want to be sure that the memory is coherent prior to writing to the
breadcrumb. This should be guaranteed by the post-sync operation, but
for that little bit of extra paranoia, split the flush into two and have
the breadcrumb write separate and explicitly wait on the prior
pipecontrol completion.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index c99017e3c3c9..c4e6bad5e6dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -412,8 +412,12 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
*cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE |
+ PIPE_CONTROL_DC_FLUSH_ENABLE);
+ *cs++ = 0;
+ *cs++ = 0;
+
+ *cs++ = GFX_OP_PIPE_CONTROL(4);
+ *cs++ = (PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt
2020-02-08 22:01 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Split the gen7 rcs flush into phases Chris Wilson
@ 2020-02-08 22:01 ` Chris Wilson
2020-02-10 21:27 ` Rodrigo Vivi
2020-02-08 23:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2020-02-08 22:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Full-ppgtt on gen7 is proving to be highly unstable and not robust.
Fixes: 3cd6e8860ecd ("drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 24b1f0ce8743..1d678aa7d420 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -437,7 +437,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.has_rps = true, \
- .ppgtt_type = INTEL_PPGTT_FULL, \
+ .ppgtt_type = INTEL_PPGTT_ALIASING, \
.ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
@@ -494,7 +494,7 @@ static const struct intel_device_info vlv_info = {
.has_rps = true,
.display.has_gmch = 1,
.display.has_hotplug = 1,
- .ppgtt_type = INTEL_PPGTT_FULL,
+ .ppgtt_type = INTEL_PPGTT_ALIASING,
.ppgtt_size = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
2020-02-08 22:01 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Split the gen7 rcs flush into phases Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt Chris Wilson
@ 2020-02-08 23:14 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-02-08 23:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
URL : https://patchwork.freedesktop.org/series/73202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7892 -> Patchwork_16498
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/index.html
Known issues
------------
Here are the changes found in Patchwork_16498 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_active:
- fi-whl-u: [PASS][1] -> [DMESG-FAIL][2] ([i915#666])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-whl-u/igt@i915_selftest@live_active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-whl-u/igt@i915_selftest@live_active.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bwr-2160: [PASS][3] -> [FAIL][4] ([i915#34])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank.html
#### Possible fixes ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [TIMEOUT][5] ([fdo#112271]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
* igt@gem_exec_parallel@fds:
- fi-byt-n2820: [FAIL][7] ([i915#694]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-byt-n2820/igt@gem_exec_parallel@fds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-byt-n2820/igt@gem_exec_parallel@fds.html
* igt@gem_exec_suspend@basic-s0:
- fi-cml-s: [FAIL][9] ([fdo#103375]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-cml-s/igt@gem_exec_suspend@basic-s0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-cml-s/igt@gem_exec_suspend@basic-s0.html
* igt@i915_module_load@reload:
- fi-skl-6770hq: [DMESG-WARN][11] ([i915#92]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-skl-6770hq/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-skl-6770hq/igt@i915_module_load@reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][13] ([i915#725]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-ivb-3770/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][15] ([i915#553] / [i915#725]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-hsw-4770/igt@i915_selftest@live_blt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [INCOMPLETE][17] ([i915#424]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111096] / [i915#323]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-skl-6770hq: [SKIP][21] ([fdo#109271]) -> [PASS][22] +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-skl-6770hq: [DMESG-WARN][23] ([i915#106] / [i915#188]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-cml-s: [FAIL][25] ([fdo#103375]) -> [INCOMPLETE][26] ([i915#1078] / [i915#283])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7892/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106
[i915#1078]: https://gitlab.freedesktop.org/drm/intel/issues/1078
[i915#188]: https://gitlab.freedesktop.org/drm/intel/issues/188
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (44 -> 39)
------------------------------
Additional (6): fi-bxt-dsi fi-bdw-5557u fi-snb-2520m fi-ilk-650 fi-blb-e6850 fi-skl-6600u
Missing (11): fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u fi-skl-lmem fi-byt-clapper fi-kbl-r fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7892 -> Patchwork_16498
CI-20190529: 20190529
CI_DRM_7892: c53ff44eb14e48089e25c34874b318e8f0d11c4c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5427: b7aaa77467742b977b1ea8716d90c7a9a2768220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16498: 5e65fd13d5be8530d6d0a967e88beda502ffef76 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5e65fd13d5be drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt
8ce13e18abf4 drm/i915/gt: Split the gen7 rcs flush into phases
5cceaf5d5251 drm/i915/gt: Tweak gen7 xcs flushing
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16498/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt
2020-02-08 22:01 ` [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt Chris Wilson
@ 2020-02-10 21:27 ` Rodrigo Vivi
0 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2020-02-10 21:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: Jani Nikula, intel-gfx
On Sat, Feb 08, 2020 at 10:01:06PM +0000, Chris Wilson wrote:
> Full-ppgtt on gen7 is proving to be highly unstable and not robust.
>
> Fixes: 3cd6e8860ecd ("drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 24b1f0ce8743..1d678aa7d420 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -437,7 +437,7 @@ static const struct intel_device_info snb_m_gt2_info = {
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> .has_rps = true, \
> - .ppgtt_type = INTEL_PPGTT_FULL, \
> + .ppgtt_type = INTEL_PPGTT_ALIASING, \
> .ppgtt_size = 31, \
> IVB_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> @@ -494,7 +494,7 @@ static const struct intel_device_info vlv_info = {
> .has_rps = true,
> .display.has_gmch = 1,
> .display.has_hotplug = 1,
> - .ppgtt_type = INTEL_PPGTT_FULL,
> + .ppgtt_type = INTEL_PPGTT_ALIASING,
> .ppgtt_size = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> --
> 2.25.0
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-10 21:25 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-02-08 22:01 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Split the gen7 rcs flush into phases Chris Wilson
2020-02-08 22:01 ` [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt Chris Wilson
2020-02-10 21:27 ` Rodrigo Vivi
2020-02-08 23:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing Patchwork
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