[xlnx:master 47/47] drivers/net//phy/dp83867.c:304:8: warning: 'val' may be used uninitialized in this function

[kbuild test robot <lkp@intel.com>]

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tree:   https://github.com/Xilinx/linux-xlnx master
head:   a1c718babcc65c64ae7c63b14bedada2e862d54c
commit: a1c718babcc65c64ae7c63b14bedada2e862d54c [47/47] net: phy: dp83867: Convert 6 wire mode to ti,sgmii-ref-clock-output-enable
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout a1c718babcc65c64ae7c63b14bedada2e862d54c
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=sh 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings

All warnings (new ones prefixed by >>):

   drivers/net//phy/dp83867.c: In function 'dp83867_config_init':
>> drivers/net//phy/dp83867.c:304:8: warning: 'val' may be used uninitialized in this function [-Wmaybe-uninitialized]
       val |= DP83867_SGMII_TYPE;

vim +/val +304 drivers/net//phy/dp83867.c

   242	
   243	static int dp83867_config_init(struct phy_device *phydev)
   244	{
   245		struct dp83867_private *dp83867;
   246		int ret, bs;
   247		u16 val, delay, cfg2;
   248	
   249		if (!phydev->priv) {
   250			dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
   251					       GFP_KERNEL);
   252			if (!dp83867)
   253				return -ENOMEM;
   254	
   255			phydev->priv = dp83867;
   256			ret = dp83867_of_init(phydev);
   257			if (ret)
   258				return ret;
   259		} else {
   260			dp83867 = (struct dp83867_private *)phydev->priv;
   261		}
   262	
   263		/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
   264		if (dp83867->rxctrl_strap_quirk) {
   265			val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
   266			val &= ~BIT(7);
   267			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
   268		}
   269	
   270		if (phy_interface_is_rgmii(phydev)) {
   271			ret = phy_write(phydev, MII_DP83867_PHYCTRL,
   272				(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
   273				(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
   274			if (ret)
   275				return ret;
   276	
   277			val = phy_read(phydev, MII_DP83867_PHYCTRL);
   278			if (val < 0)
   279				return val;
   280			val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
   281			val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
   282	
   283			/* The code below checks if "port mirroring" N/A MODE4 has been
   284			 * enabled during power on bootstrap.
   285			 *
   286			 * Such N/A mode enabled by mistake can put PHY IC in some
   287			 * internal testing mode and disable RGMII transmission.
   288			 *
   289			 * In this particular case one needs to check STRAP_STS1
   290			 * register's bit 11 (marked as RESERVED).
   291			 */
   292	
   293			bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
   294			if (bs & DP83867_STRAP_STS1_RESERVED)
   295				val &= ~DP83867_PHYCR_RESERVED_MASK;
   296	
   297			ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
   298			if (ret)
   299				return ret;
   300	
   301		} else {
   302			/* Set SGMIICTL1 6-wire mode */
   303			if (dp83867->sgmii_ref_clk_en)
 > 304				val |= DP83867_SGMII_TYPE;
   305			else
   306				val &= ~DP83867_SGMII_TYPE;
   307	
   308			phy_write_mmd(phydev, DP83867_DEVADDR,
   309				      DP83867_SGMIICTL, val);
   310	
   311			phy_write(phydev, MII_BMCR,
   312				  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
   313	
   314			cfg2 = phy_read(phydev, MII_DP83867_CFG2);
   315			cfg2 &= MII_DP83867_CFG2_MASK;
   316			cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
   317				 MII_DP83867_CFG2_SGMII_AUTONEGEN |
   318				 MII_DP83867_CFG2_SPEEDOPT_ENH |
   319				 MII_DP83867_CFG2_SPEEDOPT_CNT |
   320				 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
   321			phy_write(phydev, MII_DP83867_CFG2, cfg2);
   322	
   323			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, 0x0);
   324	
   325			phy_write(phydev, MII_DP83867_PHYCTRL,
   326				  DP83867_PHYCTRL_SGMIIEN |
   327				  (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
   328				  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
   329				  (dp83867->fifo_depth  << DP83867_PHYCTRL_TXFIFO_SHIFT));
   330			phy_write(phydev, MII_DP83867_BISCR, 0x0);
   331	
   332			/* This is a SW workaround for link instability if
   333			 * RX_CTRL is not strapped to mode 3 or 4 in HW.
   334			 */
   335			if (dp83867->rxctrl_strap_quirk) {
   336				val = phy_read_mmd(phydev, DP83867_DEVADDR,
   337						   DP83867_CFG4);
   338				val &= ~DP83867_CFG4_RESVDBIT7;
   339				val |= DP83867_CFG4_RESVDBIT8;
   340				val &= ~DP83867_CFG4_SGMII_AUTONEG_TIMER_MASK;
   341				val |= DP83867_CFG4_SGMII_AUTONEG_TIMER_11MS;
   342				phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
   343					      val);
   344			}
   345		}
   346	
   347		if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
   348		    (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
   349			val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
   350	
   351			if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
   352				val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
   353	
   354			if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
   355				val |= DP83867_RGMII_TX_CLK_DELAY_EN;
   356	
   357			if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
   358				val |= DP83867_RGMII_RX_CLK_DELAY_EN;
   359	
   360			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
   361	
   362			delay = (dp83867->rx_id_delay |
   363				(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
   364	
   365			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
   366				      delay);
   367	
   368			if (dp83867->io_impedance >= 0) {
   369				val = phy_read_mmd(phydev, DP83867_DEVADDR,
   370						   DP83867_IO_MUX_CFG);
   371	
   372				val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
   373				val |= dp83867->io_impedance &
   374				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
   375	
   376				phy_write_mmd(phydev, DP83867_DEVADDR,
   377					      DP83867_IO_MUX_CFG, val);
   378			}
   379		}
   380	
   381		/* Enable Interrupt output INT_OE in CFG3 register */
   382		if (phy_interrupt_is_valid(phydev)) {
   383			val = phy_read(phydev, DP83867_CFG3);
   384			val |= BIT(7);
   385			phy_write(phydev, DP83867_CFG3, val);
   386		}
   387	
   388		if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
   389			dp83867_config_port_mirroring(phydev);
   390	
   391		/* Clock output selection if muxing property is set */
   392		if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
   393			val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
   394			val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
   395			val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
   396			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
   397		}
   398	
   399		return 0;
   400	}
   401	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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