[PATCH 1/1] iommu/amd: Fix the configuration of GCR3 table root pointer

[PATCH 1/1] iommu/amd: Fix the configuration of GCR3 table root pointer

[Adrian Huang]

From: Adrian Huang <ahuang12@lenovo.com>

The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
this requires 21 bits (Please see the AMD IOMMU specification).
This leads to the potential failure when the bit 51 of SPA of
the GCR3 table root pointer is 1'.

Signed-off-by: Adrian Huang <ahuang12@lenovo.com>
---
 drivers/iommu/amd_iommu_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index f8d01d6b00da..ca8c4522045b 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -348,7 +348,7 @@
 
 #define DTE_GCR3_VAL_A(x)	(((x) >> 12) & 0x00007ULL)
 #define DTE_GCR3_VAL_B(x)	(((x) >> 15) & 0x0ffffULL)
-#define DTE_GCR3_VAL_C(x)	(((x) >> 31) & 0xfffffULL)
+#define DTE_GCR3_VAL_C(x)	(((x) >> 31) & 0x1fffffULL)
 
 #define DTE_GCR3_INDEX_A	0
 #define DTE_GCR3_INDEX_B	1
-- 
2.17.1

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Re: [PATCH 1/1] iommu/amd: Fix the configuration of GCR3 table root pointer

[Joerg Roedel]

On Fri, Feb 14, 2020 at 06:44:51PM +0800, Adrian Huang wrote:
> From: Adrian Huang <ahuang12@lenovo.com>
> 
> The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
> this requires 21 bits (Please see the AMD IOMMU specification).
> This leads to the potential failure when the bit 51 of SPA of
> the GCR3 table root pointer is 1'.
> 
> Signed-off-by: Adrian Huang <ahuang12@lenovo.com>

Applied, thanks.
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